| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Support Intel AMX-COMPLEX | Haochen Jiang | 2023-04-07 | 1 | -0/+3 |
| * | x86: drop "shimm" special case template expansions | Jan Beulich | 2023-03-20 | 1 | -15/+15 |
| * | x86: VexVVVV is now merely a boolean | Jan Beulich | 2023-03-20 | 1 | -194/+196 |
| * | x86: re-work build_modrm_byte()'s register assignment | Jan Beulich | 2023-03-20 | 1 | -13/+13 |
| * | x86: MONITOR/MWAIT are not SSE3 insns | Jan Beulich | 2023-02-24 | 1 | -5/+5 |
| * | x86-64: don't permit LAHF/SAHF with "generic64" | Jan Beulich | 2023-02-24 | 1 | -2/+4 |
| * | x86: have insns acting on segment selector values allow for consistent operands | Jan Beulich | 2023-02-24 | 1 | -5/+10 |
| * | x86: restrict insn templates accepting negative 8-bit immediates | Jan Beulich | 2023-02-24 | 1 | -58/+58 |
| * | x86-64: LAR and LSL don't need REX.W | Jan Beulich | 2023-02-22 | 1 | -4/+4 |
| * | x86: optimize BT{,C,R,S} $imm,%reg | Jan Beulich | 2023-02-22 | 1 | -4/+4 |
| * | x86: {LD,ST}TILECFG use an extension opcode | Jan Beulich | 2023-02-14 | 1 | -2/+2 |
| * | PR30120: fix x87 fucomp misassembled | Michael Matz | 2023-02-13 | 1 | -1/+1 |
| * | x86: drop use of VEX3SOURCES | Jan Beulich | 2023-02-10 | 1 | -32/+32 |
| * | x86: drop use of XOP2SOURCES | Jan Beulich | 2023-02-10 | 1 | -3/+3 |
| * | x86: limit use of XOP2SOURCES | Jan Beulich | 2023-02-10 | 1 | -1/+1 |
| * | x86: use ModR/M for FPU insns with operands | Jan Beulich | 2023-01-27 | 1 | -72/+72 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2023-01-01 | 1 | -1/+1 |
| * | x86: rename CheckRegSize to CheckOperandSize | Jan Beulich | 2022-12-21 | 1 | -507/+507 |
| * | x86: omit Cpu prefixes from opcode table | Jan Beulich | 2022-12-19 | 1 | -1874/+1889 |
| * | x86: change representation of extension opcode | Jan Beulich | 2022-12-16 | 1 | -2281/+2280 |
| * | x86: further re-work insn/suffix recognition to also cover MOVSX | Jan Beulich | 2022-12-12 | 1 | -8/+3 |
| * | x86: drop (now) stray IsString | Jan Beulich | 2022-12-12 | 1 | -13/+13 |
| * | x86: re-work insn/suffix recognition | Jan Beulich | 2022-12-12 | 1 | -15/+4 |
| * | x86: Allow 16-bit register source for LAR and LSL | H.J. Lu | 2022-12-03 | 1 | -2/+2 |
| * | x86: also use D for XCHG and TEST | Jan Beulich | 2022-12-02 | 1 | -6/+3 |
| * | x86: drop No_ldSuf | Jan Beulich | 2022-12-01 | 1 | -445/+445 |
| * | x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX | Jan Beulich | 2022-12-01 | 1 | -2/+2 |
| * | x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX | Jan Beulich | 2022-12-01 | 1 | -4/+4 |
| * | x86: clean up after removal of support for gcc <= 2.8.1 | Jan Beulich | 2022-11-30 | 1 | -4/+3 |
| * | x86: drop FloatR | Jan Beulich | 2022-11-30 | 1 | -8/+4 |
| * | x86: widen applicability and use of CheckRegSize | Jan Beulich | 2022-11-24 | 1 | -7/+7 |
| * | x86: add missing CheckRegSize | Jan Beulich | 2022-11-24 | 1 | -3/+3 |
| * | x86: correct handling of LAR and LSL | Jan Beulich | 2022-11-24 | 1 | -2/+4 |
| * | opcodes: Define NoSuf in i386-opc.tbl | H.J. Lu | 2022-11-17 | 1 | -1847/+1848 |
| * | Add AMD znver4 processor support | Tejas Joshi | 2022-11-15 | 1 | -0/+7 |
| * | x86: fold special-operand insn attributes into a single enum | Jan Beulich | 2022-11-14 | 1 | -2/+11 |
| * | x86: drop stray IsString from PadLock insns | Jan Beulich | 2022-11-11 | 1 | -16/+16 |
| * | Support Intel RAO-INT | Kong Lingling | 2022-11-08 | 1 | -0/+9 |
| * | Support Intel AVX-NE-CONVERT | konglin1 | 2022-11-04 | 1 | -0/+12 |
| * | i386: Rename <xy> template. | konglin1 | 2022-11-04 | 1 | -17/+18 |
| * | x86: drop bogus Tbyte | Jan Beulich | 2022-11-02 | 1 | -2/+2 |
| * | Support Intel MSRLIST | Hu, Lin1 | 2022-11-02 | 1 | -0/+7 |
| * | Support Intel WRMSRNS | Hu, Lin1 | 2022-11-02 | 1 | -0/+6 |
| * | Support Intel CMPccXADD | Haochen Jiang | 2022-11-02 | 1 | -0/+6 |
| * | Support Intel AVX-VNNI-INT8 | Cui,Lili | 2022-11-02 | 1 | -0/+11 |
| * | Support Intel AVX-IFMA | Hongyu Wang | 2022-11-02 | 1 | -0/+7 |
| * | Support Intel PREFETCHI | Cui, Lili | 2022-10-31 | 1 | -0/+7 |
| * | Support Intel AMX-FP16 | Cui,Lili | 2022-10-21 | 1 | -0/+1 |
| * | x86: re-work AVX-VNNI support | Jan Beulich | 2022-10-20 | 1 | -10/+10 |
| * | x86/Intel: restrict suffix derivation | Jan Beulich | 2022-09-30 | 1 | -155/+145 |
