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path: root/opcodes/i386-opc.h
Commit message (Expand)AuthorAgeFilesLines
* Add AMD znver4 processor supportTejas Joshi2022-11-151-0/+3
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-141-32/+22
* Support Intel RAO-INTKong Lingling2022-11-081-0/+3
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-0/+3
* Support Intel MSRLISTHu, Lin12022-11-021-0/+3
* Support Intel WRMSRNSHu, Lin12022-11-021-0/+3
* Support Intel CMPccXADDHaochen Jiang2022-11-021-1/+4
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-1/+4
* Support Intel AVX-IFMAHongyu Wang2022-11-021-0/+3
* Support Intel PREFETCHICui, Lili2022-10-311-0/+3
* Support Intel AMX-FP16Cui,Lili2022-10-211-0/+3
* x86: re-work AVX-VNNI supportJan Beulich2022-10-201-3/+0
* x86/Intel: restrict suffix derivationJan Beulich2022-09-301-6/+0
* x86: also use D for MOVBEJan Beulich2022-08-031-1/+1
* x86: re-order insn template fieldsJan Beulich2022-07-181-3/+11
* x86: make D attribute usable for XOP and FMA4 insnsJan Beulich2022-07-061-0/+3
* x86: fold Disp32S and Disp32Jan Beulich2022-07-041-4/+1
* x86: never set i386_cpu_flags' "unused" fieldJan Beulich2022-03-171-0/+4
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-171-6/+0
* x86: drop NoAVX insn attributeJan Beulich2022-01-061-3/+0
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-0/+11
* C99 opcodes configuryAlan Modra2021-04-051-3/+0
* x86: drop seg_entryJan Beulich2021-03-301-14/+1
* x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2021-03-301-5/+0
* x86: adjust st(<N>) parsingJan Beulich2021-03-301-3/+3
* x86: shrink some struct insn_template fieldsJan Beulich2021-03-291-4/+4
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-3/+0
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-8/+11
* x86: re-number PREFIX_0X<nn>Jan Beulich2021-03-231-5/+6
* x86: re-order two fields of struct insn_templateJan Beulich2021-03-231-3/+3
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-16/+21
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-20/+11
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-0/+9
* Enhancement for avx-vnni patchCui,Lili2020-10-161-3/+3
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-0/+6
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-0/+3
* x86: Support Intel UINTRLili Cui2020-10-141-0/+3
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-2/+12
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+3
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+6
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-0/+12
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-1/+15
* x86: Add SwapSourcesH.J. Lu2020-07-021-0/+4
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-6/+6
* x86: restrict use of register aliasesJan Beulich2020-06-081-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+3
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+3
* x86: drop Rex64 attributeJan Beulich2020-03-061-3/+0