| Commit message (Expand) | Author | Age | Files | Lines |
* | Add AMD znver4 processor support | Tejas Joshi | 2022-11-15 | 1 | -0/+3 |
* | x86: fold special-operand insn attributes into a single enum | Jan Beulich | 2022-11-14 | 1 | -32/+22 |
* | Support Intel RAO-INT | Kong Lingling | 2022-11-08 | 1 | -0/+3 |
* | Support Intel AVX-NE-CONVERT | konglin1 | 2022-11-04 | 1 | -0/+3 |
* | Support Intel MSRLIST | Hu, Lin1 | 2022-11-02 | 1 | -0/+3 |
* | Support Intel WRMSRNS | Hu, Lin1 | 2022-11-02 | 1 | -0/+3 |
* | Support Intel CMPccXADD | Haochen Jiang | 2022-11-02 | 1 | -1/+4 |
* | Support Intel AVX-VNNI-INT8 | Cui,Lili | 2022-11-02 | 1 | -1/+4 |
* | Support Intel AVX-IFMA | Hongyu Wang | 2022-11-02 | 1 | -0/+3 |
* | Support Intel PREFETCHI | Cui, Lili | 2022-10-31 | 1 | -0/+3 |
* | Support Intel AMX-FP16 | Cui,Lili | 2022-10-21 | 1 | -0/+3 |
* | x86: re-work AVX-VNNI support | Jan Beulich | 2022-10-20 | 1 | -3/+0 |
* | x86/Intel: restrict suffix derivation | Jan Beulich | 2022-09-30 | 1 | -6/+0 |
* | x86: also use D for MOVBE | Jan Beulich | 2022-08-03 | 1 | -1/+1 |
* | x86: re-order insn template fields | Jan Beulich | 2022-07-18 | 1 | -3/+11 |
* | x86: make D attribute usable for XOP and FMA4 insns | Jan Beulich | 2022-07-06 | 1 | -0/+3 |
* | x86: fold Disp32S and Disp32 | Jan Beulich | 2022-07-04 | 1 | -4/+1 |
* | x86: never set i386_cpu_flags' "unused" field | Jan Beulich | 2022-03-17 | 1 | -0/+4 |
* | x86: drop L1OM/K1OM support from gas | Jan Beulich | 2022-03-17 | 1 | -6/+0 |
* | x86: drop NoAVX insn attribute | Jan Beulich | 2022-01-06 | 1 | -3/+0 |
* | Update year range in copyright notice of binutils files | Alan Modra | 2022-01-02 | 1 | -1/+1 |
* | [PATCH 1/2] Enable Intel AVX512_FP16 instructions | Cui,Lili | 2021-08-05 | 1 | -0/+11 |
* | C99 opcodes configury | Alan Modra | 2021-04-05 | 1 | -3/+0 |
* | x86: drop seg_entry | Jan Beulich | 2021-03-30 | 1 | -14/+1 |
* | x86: drop REGNAM_{AL,AX,EAX} | Jan Beulich | 2021-03-30 | 1 | -5/+0 |
* | x86: adjust st(<N>) parsing | Jan Beulich | 2021-03-30 | 1 | -3/+3 |
* | x86: shrink some struct insn_template fields | Jan Beulich | 2021-03-29 | 1 | -4/+4 |
* | x86: derive opcode length from opcode value | Jan Beulich | 2021-03-24 | 1 | -3/+0 |
* | x86: don't use opcode_length to identify pseudo prefixes | Jan Beulich | 2021-03-24 | 1 | -8/+11 |
* | x86: re-number PREFIX_0X<nn> | Jan Beulich | 2021-03-23 | 1 | -5/+6 |
* | x86: re-order two fields of struct insn_template | Jan Beulich | 2021-03-23 | 1 | -3/+3 |
* | x86: split opcode prefix and opcode space representation | Jan Beulich | 2021-03-23 | 1 | -16/+21 |
* | x86: fold some prefix related attributes into a single one | Jan Beulich | 2021-03-09 | 1 | -20/+11 |
* | Update year range in copyright notice of binutils files | Alan Modra | 2021-01-01 | 1 | -1/+1 |
* | Add AMD znver3 processor support | Ganesh Gopalasubramanian | 2020-10-20 | 1 | -0/+9 |
* | Enhancement for avx-vnni patch | Cui,Lili | 2020-10-16 | 1 | -3/+3 |
* | x86: Support Intel AVX VNNI | H.J. Lu | 2020-10-14 | 1 | -0/+6 |
* | x86: Add support for Intel HRESET instruction | Lili Cui | 2020-10-14 | 1 | -0/+3 |
* | x86: Support Intel UINTR | Lili Cui | 2020-10-14 | 1 | -0/+3 |
* | x86: Rename VexOpcode to OpcodePrefix | H.J. Lu | 2020-10-13 | 1 | -2/+12 |
* | Add support for Intel TDX instructions. | Cui,Lili | 2020-09-24 | 1 | -0/+3 |
* | Enable support to Intel Keylocker instructions | Terry Guo | 2020-09-23 | 1 | -0/+6 |
* | x86: Add {disp16} pseudo prefix | H.J. Lu | 2020-07-30 | 1 | -0/+12 |
* | x86: Add support for Intel AMX instructions | Lili Cui | 2020-07-10 | 1 | -1/+15 |
* | x86: Add SwapSources | H.J. Lu | 2020-07-02 | 1 | -0/+4 |
* | x86: Rename VecSIB to SIB for Intel AMX | H.J. Lu | 2020-06-26 | 1 | -6/+6 |
* | x86: restrict use of register aliases | Jan Beulich | 2020-06-08 | 1 | -1/+1 |
* | Add support for intel TSXLDTRK instructions$ | Cui,Lili | 2020-04-07 | 1 | -0/+3 |
* | Add support for intel SERIALIZE instruction | LiliCui | 2020-04-02 | 1 | -0/+3 |
* | x86: drop Rex64 attribute | Jan Beulich | 2020-03-06 | 1 | -3/+0 |