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| author | Jan Beulich <jbeulich@suse.com> | 2022-03-17 11:02:42 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-03-17 11:02:42 +0100 |
| commit | c085ab00c7b2877e35420ee196d24f9eeb9233f4 (patch) | |
| tree | 318b3ed8b81f3a298b1e7543ac597e5bbc35c76a /opcodes/i386-opc.h | |
| parent | 648d04db39d0f8d69d5f4d47a86c7bd9ecc10e85 (diff) | |
| download | binutils-gdb-c085ab00c7b2877e35420ee196d24f9eeb9233f4.tar.gz | |
x86: drop L1OM/K1OM support from gas
This was only rudimentary support anyway; none of the sub-architecture
specific insns were ever supported.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index ff2eaa2d457..a7acaebe4bd 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -111,10 +111,6 @@ enum CpuAVX512DQ, /* Intel AVX-512 BW Instructions support required. */ CpuAVX512BW, - /* Intel L1OM support required */ - CpuL1OM, - /* Intel K1OM support required */ - CpuK1OM, /* Intel IAMCU support required */ CpuIAMCU, /* Xsave/xrstor New Instructions support required */ @@ -340,8 +336,6 @@ typedef union i386_cpu_flags unsigned int cpuavx512vl:1; unsigned int cpuavx512dq:1; unsigned int cpuavx512bw:1; - unsigned int cpul1om:1; - unsigned int cpuk1om:1; unsigned int cpuiamcu:1; unsigned int cpuxsave:1; unsigned int cpuxsaveopt:1; |