summaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.h
Commit message (Expand)AuthorAgeFilesLines
* Support Intel AMX-COMPLEXHaochen Jiang2023-04-071-0/+3
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-311-0/+2
* x86: VexVVVV is now merely a booleanJan Beulich2023-03-201-17/+2
* x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich2023-02-241-0/+3
* x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich2023-02-241-0/+3
* x86: drop use of VEX3SOURCESJan Beulich2023-02-101-7/+0
* x86: drop use of XOP2SOURCESJan Beulich2023-02-101-2/+0
* x86: move (and rename) opcodespace attributeJan Beulich2023-02-101-25/+23
* x86: use ModR/M for FPU insns with operandsJan Beulich2023-01-271-2/+2
* x86: embed register names in reg_entryJan Beulich2023-01-201-1/+1
* x86: move insn mnemonics to a separate tableJan Beulich2023-01-201-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* x86: rename CheckRegSize to CheckOperandSizeJan Beulich2022-12-211-3/+3
* x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich2022-12-121-6/+1
* x86: drop No_ldSufJan Beulich2022-12-011-3/+0
* x86: drop FloatRJan Beulich2022-11-301-3/+0
* i386: Move i386_seg_prefixes to gasH.J. Lu2022-11-171-1/+0
* Add AMD znver4 processor supportTejas Joshi2022-11-151-0/+3
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-141-32/+22
* Support Intel RAO-INTKong Lingling2022-11-081-0/+3
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-0/+3
* Support Intel MSRLISTHu, Lin12022-11-021-0/+3
* Support Intel WRMSRNSHu, Lin12022-11-021-0/+3
* Support Intel CMPccXADDHaochen Jiang2022-11-021-1/+4
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-1/+4
* Support Intel AVX-IFMAHongyu Wang2022-11-021-0/+3
* Support Intel PREFETCHICui, Lili2022-10-311-0/+3
* Support Intel AMX-FP16Cui,Lili2022-10-211-0/+3
* x86: re-work AVX-VNNI supportJan Beulich2022-10-201-3/+0
* x86/Intel: restrict suffix derivationJan Beulich2022-09-301-6/+0
* x86: also use D for MOVBEJan Beulich2022-08-031-1/+1
* x86: re-order insn template fieldsJan Beulich2022-07-181-3/+11
* x86: make D attribute usable for XOP and FMA4 insnsJan Beulich2022-07-061-0/+3
* x86: fold Disp32S and Disp32Jan Beulich2022-07-041-4/+1
* x86: never set i386_cpu_flags' "unused" fieldJan Beulich2022-03-171-0/+4
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-171-6/+0
* x86: drop NoAVX insn attributeJan Beulich2022-01-061-3/+0
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-0/+11
* C99 opcodes configuryAlan Modra2021-04-051-3/+0
* x86: drop seg_entryJan Beulich2021-03-301-14/+1
* x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2021-03-301-5/+0
* x86: adjust st(<N>) parsingJan Beulich2021-03-301-3/+3
* x86: shrink some struct insn_template fieldsJan Beulich2021-03-291-4/+4
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-3/+0
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-8/+11
* x86: re-number PREFIX_0X<nn>Jan Beulich2021-03-231-5/+6
* x86: re-order two fields of struct insn_templateJan Beulich2021-03-231-3/+3
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-16/+21
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-20/+11
View Lorry Controller Status