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* Revert "segfault at i386-dis.c:9815"Alan Modra2023-03-201-9/+4
* segfault at i386-dis.c:9815Alan Modra2023-03-191-4/+9
* x86: embed register and alike names in disassemblerJan Beulich2023-01-201-34/+34
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ...Jan Beulich2022-12-121-2/+14
* x86: Remove unnecessary vex.w check for xh_mode in disassemblerHaochen Jiang2022-12-061-17/+12
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-031-14/+2
* x86: correct handling of LAR and LSLJan Beulich2022-11-241-2/+14
* Add AMD znver4 processor supportTejas Joshi2022-11-151-1/+15
* x86: Correct wrong comments in vex_w_tableHaochen Jiang2022-11-081-1/+1
* Support Intel RAO-INTKong Lingling2022-11-081-1/+10
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-3/+43
* Support Intel MSRLISTHu, Lin12022-11-021-0/+17
* Support Intel WRMSRNSHu, Lin12022-11-021-0/+7
* Support Intel CMPccXADDHaochen Jiang2022-11-021-17/+130
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-3/+20
* Support Intel AVX-IFMAHongyu Wang2022-11-021-2/+14
* Support Intel PREFETCHICui, Lili2022-10-311-2/+76
* x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich2022-10-241-86/+122
* Support Intel AMX-FP16Cui,Lili2022-10-211-0/+18
* x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich2022-10-171-11/+18
* x86: avoid i386_dis_printf()'s staging area for a fair part of outputJan Beulich2022-09-121-20/+24
* i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu2022-08-161-3/+6
* Get rid of fprintf_vma and sprintf_vmaAlan Modra2022-08-011-17/+4
* x86: drop print_operand_value()'s "hex" parameterJan Beulich2022-06-151-55/+16
* x86: fix incorrect indirectionJan Beulich2022-06-131-1/+1
* x86: replace global scratch bufferJan Beulich2022-06-131-126/+97
* x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich2022-06-131-6/+8
* x86: shrink prefix related disassembler state fieldsJan Beulich2022-06-131-27/+28
* x86: properly initialize struct instr_info instance(s)Jan Beulich2022-06-131-257/+235
* libopcodes: extend the styling within the i386 disassemblerAndrew Burgess2022-06-081-137/+286
* opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess2022-05-271-5/+22
* x86/Intel: adjust representation of embedded rounding / SAEJan Beulich2022-05-271-0/+17
* x86/Intel: adjust representation of embedded broadcastJan Beulich2022-05-271-4/+11
* x86: shrink op_riprelJan Beulich2022-05-181-18/+12
* Fix multiple ubsan warnings in i386-dis.cAlan Modra2022-05-071-13/+13
* x86: correct and simplify NOP disassemblyJan Beulich2022-04-191-21/+9
* opcodes/i386: partially implement disassembler style supportAndrew Burgess2022-04-041-23/+40
* x86: drop L1OM special case from disassemblerJan Beulich2022-03-241-6/+2
* x86: Add has_sib to struct instr_infoH.J. Lu2022-02-151-8/+9
* x86: adjust struct instr_info field typesJan Beulich2022-01-171-36/+39
* x86: drop index16 fieldJan Beulich2022-01-171-5/+3
* x86: drop most Intel syntax register name arraysJan Beulich2022-01-171-230/+119
* x86: fold variables in memory operand index handlingJan Beulich2022-01-171-19/+15
* x86: constify disassembler static dataJan Beulich2022-01-171-58/+58
* x86: drop ymmxmm_modeJan Beulich2022-01-141-16/+0
* x86: share yet more VEX table entries with EVEX decodingJan Beulich2022-01-141-73/+53
* x86: record further wrong uses of EVEX.bJan Beulich2022-01-141-0/+8
* x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-41/+1
* x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-33/+39
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