x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns

When no AVX512-specific functionality is in use, the disassembly of
AVX512VL insns is indistinguishable from their AVX counterparts (if such
exist). Emit the {evex} pseudo-prefix in such cases.

Where applicable drop stray uses of PREFIX_OPCODE from table entries.

1 files changed, 122 insertions, 86 deletions

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index fce05e07eea..d94d6ad8464 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1759,6 +1759,8 @@ struct dis386 {
    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
    "XV" => print "{vex} " pseudo prefix
+   "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
+	   is used by an EVEX-encoded (AVX512VL) instruction.
    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
 	   being false, or no operand at all in 64bit mode, or if suffix_always
 	   is true.
@@ -3564,71 +3566,71 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F10 */
   {
-    { "vmovupX",	{ XM, EXEvexXNoBcst }, PREFIX_OPCODE },
-    { "vmovs%XS",	{ XMScalar, VexScalarR, EXd }, 0 },
-    { "vmovupX",	{ XM, EXEvexXNoBcst }, PREFIX_OPCODE },
-    { "vmovs%XD",	{ XMScalar, VexScalarR, EXq }, 0 },
+    { "%XEvmovupX",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovs%XS",	{ XMScalar, VexScalarR, EXd }, 0 },
+    { "%XEvmovupX",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovs%XD",	{ XMScalar, VexScalarR, EXq }, 0 },
   },
 
   /* PREFIX_VEX_0F11 */
   {
-    { "vmovupX",	{ EXxS, XM }, PREFIX_OPCODE },
-    { "vmovs%XS",	{ EXdS, VexScalarR, XMScalar }, 0 },
-    { "vmovupX",	{ EXxS, XM }, PREFIX_OPCODE },
-    { "vmovs%XD",	{ EXqS, VexScalarR, XMScalar }, 0 },
+    { "%XEvmovupX",	{ EXxS, XM }, 0 },
+    { "%XEvmovs%XS",	{ EXdS, VexScalarR, XMScalar }, 0 },
+    { "%XEvmovupX",	{ EXxS, XM }, 0 },
+    { "%XEvmovs%XD",	{ EXqS, VexScalarR, XMScalar }, 0 },
   },
 
   /* PREFIX_VEX_0F12 */
   {
     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
-    { "vmov%XSldup",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmov%XSldup",	{ XM, EXEvexXNoBcst }, 0 },
     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
-    { "vmov%XDdup",	{ XM, EXymmq }, 0 },
+    { "%XEvmov%XDdup",	{ XM, EXymmq }, 0 },
   },
 
   /* PREFIX_VEX_0F16 */
   {
     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
-    { "vmov%XShdup",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmov%XShdup",	{ XM, EXEvexXNoBcst }, 0 },
     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
   },
 
   /* PREFIX_VEX_0F2A */
   {
     { Bad_Opcode },
-    { "vcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "%XEvcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
     { Bad_Opcode },
-    { "vcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
+    { "%XEvcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
   },
 
   /* PREFIX_VEX_0F2C */
   {
     { Bad_Opcode },
-    { "vcvttss2si",	{ Gdq, EXd, EXxEVexS }, 0 },
+    { "%XEvcvttss2si",	{ Gdq, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vcvttsd2si",	{ Gdq, EXq, EXxEVexS }, 0 },
+    { "%XEvcvttsd2si",	{ Gdq, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F2D */
   {
     { Bad_Opcode },
-    { "vcvtss2si",	{ Gdq, EXd, EXxEVexR }, 0 },
+    { "%XEvcvtss2si",	{ Gdq, EXd, EXxEVexR }, 0 },
     { Bad_Opcode },
-    { "vcvtsd2si",	{ Gdq, EXq, EXxEVexR }, 0 },
+    { "%XEvcvtsd2si",	{ Gdq, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F2E */
   {
-    { "vucomisX",	{ XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvucomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vucomisX",	{ XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvucomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F2F */
   {
-    { "vcomisX",	{ XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvcomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vcomisX",	{ XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvcomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -3743,10 +3745,10 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F51 */
   {
-    { "vsqrtpX",	{ XM, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsqrts%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vsqrtpX",	{ XM, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsqrts%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvsqrtpX",	{ XM, EXx, EXxEVexR }, 0 },
+    { "%XEvsqrts%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvsqrtpX",	{ XM, EXx, EXxEVexR }, 0 },
+    { "%XEvsqrts%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F52 */
@@ -3763,26 +3765,26 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F58 */
   {
-    { "vaddpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vadds%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vaddpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vadds%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvaddpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvadds%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvaddpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvadds%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F59 */
   {
-    { "vmulpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vmuls%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vmulpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vmuls%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvmulpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvmuls%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvmulpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvmuls%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5A */
   {
-    { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
-    { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
-    { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+    { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+    { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5B */
@@ -3794,34 +3796,34 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F5C */
   {
-    { "vsubpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsubs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vsubpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsubs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvsubpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvsubs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvsubpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvsubs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5D */
   {
-    { "vminpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmins%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vminpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmins%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvminpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmins%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvminpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmins%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F5E */
   {
-    { "vdivpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vdivs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vdivpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vdivs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvdivpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvdivs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvdivpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvdivs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5F */
   {
-    { "vmaxpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmaxs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vmaxpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmaxs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvmaxpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmaxs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvmaxpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmaxs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F6F */
@@ -6681,32 +6683,32 @@ static const struct dis386 vex_table[][256] = {
 static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
   {
-    { "vmovlpX",	{ XM, Vex, EXq }, PREFIX_OPCODE },
+    { "%XEvmovlpX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F12_P_0_M_1 */
   {
-    { "vmovhlp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovhlp%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F13_M_0 */
   {
-    { "vmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
   {
-    { "vmovhpX",	{ XM, Vex, EXq }, PREFIX_OPCODE },
+    { "%XEvmovhpX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F16_P_0_M_1 */
   {
-    { "vmovlhp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovlhp%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F17_M_0 */
   {
-    { "vmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F41 */
@@ -6758,7 +6760,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F6E */
   {
-    { "vmovK",		{ XMScalar, Edq }, PREFIX_DATA },
+    { "%XEvmovK",	{ XMScalar, Edq }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F77 */
@@ -6769,12 +6771,12 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F7E_P_1 */
   {
-    { "vmovq",		{ XMScalar, EXq }, 0 },
+    { "%XEvmovq",	{ XMScalar, EXq }, 0 },
   },
 
   /* VEX_LEN_0F7E_P_2 */
   {
-    { "vmovK",		{ Edq, XMScalar }, 0 },
+    { "%XEvmovK",	{ Edq, XMScalar }, 0 },
   },
 
   /* VEX_LEN_0F90 */
@@ -6819,17 +6821,17 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0FC4 */
   {
-    { "vpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
+    { "%XEvpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FC5 */
   {
-    { "vpextrw",	{ Gd, XS, Ib }, PREFIX_DATA },
+    { "%XEvpextrw",	{ Gd, XS, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FD6 */
   {
-    { "vmovq",		{ EXqS, XMScalar }, PREFIX_DATA },
+    { "%XEvmovq",	{ EXqS, XMScalar }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FF7 */
@@ -6986,22 +6988,22 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A14 */
   {
-    { "vpextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A15 */
   {
-    { "vpextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A16  */
   {
-    { "vpextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A17 */
   {
-    { "vextractps",	{ Ed, XM, Ib }, PREFIX_DATA },
+    { "%XEvextractps",	{ Ed, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A18 */
@@ -7018,17 +7020,17 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A20 */
   {
-    { "vpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
+    { "%XEvpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A21 */
   {
-    { "vinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
+    { "%XEvinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A22 */
   {
-    { "vpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
+    { "%XEvpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A30 */
@@ -7470,7 +7472,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F380C  */
-    { "vpermilps",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpermilps",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F380D  */
@@ -7494,7 +7496,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3818 */
-    { "vbroadcastss",	{ XM, EXd }, PREFIX_DATA },
+    { "%XEvbroadcastss",	{ XM, EXd }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3819_L_1 */
@@ -7570,7 +7572,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3858 */
-    { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
+    { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3859 */
@@ -7606,25 +7608,25 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3878 */
-    { "vpbroadcastb",	{ XM, EXb }, PREFIX_DATA },
+    { "%XEvpbroadcastb",	{ XM, EXb }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3879 */
-    { "vpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
+    { "%XEvpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F38CF */
-    { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A00_L_1 */
     { Bad_Opcode },
-    { "vpermq",		{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermq",		{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A01_L_1 */
     { Bad_Opcode },
-    { "vpermpd",	{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermpd",	{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A02 */
@@ -7632,7 +7634,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A04 */
-    { "vpermilps",	{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermilps",	{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A05 */
@@ -7652,7 +7654,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A1D */
-    { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
+    { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A38_L_1 */
@@ -7681,12 +7683,12 @@ static const struct dis386 vex_w_table[][2] = {
   {
     /* VEX_W_0F3ACE */
     { Bad_Opcode },
-    { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3ACF */
     { Bad_Opcode },
-    { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* VEX_W_0FXOP_08_85_L_0 */
   {
@@ -8218,7 +8220,7 @@ static const struct dis386 mod_table[][2] = {
   },
   {
     /* MOD_VEX_0F2B */
-    { "vmovntpX",	{ Mx, XM }, PREFIX_OPCODE },
+    { "%XEvmovntpX",	{ Mx, XM }, PREFIX_OPCODE },
   },
   {
     /* MOD_VEX_0F41_L_1 */
@@ -10469,7 +10471,41 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
 	  else
 	    *ins->obufp++ = 'w';
 	  break;
-	case 'E':		/* For jcxz/jecxz */
+	case 'E':
+	  if (l == 1)
+	    {
+	      switch (last[0])
+		{
+		case 'X':
+		  if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
+		      || !ins->vex.r
+		      || (ins->modrm.mod == 3 && (ins->rex & REX_X))
+		      || !ins->vex.v || ins->vex.mask_register_specifier)
+		    break;
+		  /* AVX512 extends a number of V*D insns to also have V*Q variants,
+		     merely distinguished by EVEX.W.  Look for a use of the
+		     respective macro.  */
+		  if (ins->vex.w)
+		    {
+		      const char *pct = strchr (p + 1, '%');
+
+		      if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
+			break;
+		    }
+		  *ins->obufp++ = '{';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'v';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'x';
+		  *ins->obufp++ = '}';
+		  *ins->obufp++ = ' ';
+		  break;
+		default:
+		  abort ();
+		}
+		break;
+	    }
+	  /* For jcxz/jecxz */
 	  if (ins->address_mode == mode_64bit)
 	    {
 	      if (sizeflag & AFLAG)