| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update year range in copyright notice of binutils files | Alan Modra | 2023-01-01 | 1 | -1/+1 |
| * | aarch64: Add support for Common Short Sequence Compression extension | Andre Vieira | 2022-11-14 | 1 | -1/+25 |
| * | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 2022-10-17 | 1 | -6/+15 |
| * | Arm64: support CLEARBHB alias | Jan Beulich | 2022-10-05 | 1 | -0/+1 |
| * | aarch64: Add support for new SME instructions | Richard Sandiford | 2022-01-06 | 1 | -0/+3 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2022-01-02 | 1 | -1/+1 |
| * | aarch64: Add BC instruction | Richard Sandiford | 2021-12-02 | 1 | -0/+7 |
| * | aarch64: Enforce P/M/E order for MOPS instructions | Richard Sandiford | 2021-12-02 | 1 | -6/+14 |
| * | aarch64: Add support for +mops | Richard Sandiford | 2021-12-02 | 1 | -1/+106 |
| * | aarch64: [SME] SVE2 instructions added to support SME | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+19 |
| * | aarch64: [SME] Add SME mode selection and state access instructions | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+8 |
| * | aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+46 |
| * | aarch64: [SME] Add ZERO instruction | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+4 |
| * | aarch64: [SME] Add MOV and MOVA instructions | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+19 |
| * | aarch64: [SME] Add SME instructions | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+83 |
| * | aarch64: [SME] Add +sme option to -march | Przemyslaw Wirkus | 2021-11-17 | 1 | -0/+11 |
| * | opcodes: constify aarch64_opcode_tables | Mike Frysinger | 2021-07-01 | 1 | -1/+1 |
| * | AArch64: Fix Atomic LD64/ST64 classification. | Tejas Belagod | 2021-04-09 | 1 | -4/+4 |
| * | aarch64: Remove support for CSRE | Kyrylo Tkachov | 2021-01-11 | 1 | -7/+0 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2021-01-01 | 1 | -1/+1 |
| * | aarch64: Extract Condition flag manipulation feature from Armv8.4-A | Przemyslaw Wirkus | 2020-11-16 | 1 | -4/+9 |
| * | aarch64: Allow LS64 feature with Armv8.6 | Przemyslaw Wirkus | 2020-11-11 | 1 | -1/+1 |
| * | aarch64: Limit Rt register number for LS64 load/store instructions | Przemyslaw Wirkus | 2020-11-09 | 1 | -4/+5 |
| * | aarch64: Extract Pointer Authentication feature from Armv8.3-A | Przemyslaw Wirkus | 2020-11-06 | 1 | -33/+38 |
| * | [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7 | Przemyslaw Wirkus | 2020-11-03 | 1 | -2/+16 |
| * | [PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-a | Przemyslaw Wirkus | 2020-10-30 | 1 | -0/+1 |
| * | aarch64: Add CSR PDEC instruction | Przemyslaw Wirkus | 2020-10-28 | 1 | -0/+8 |
| * | aarch64: Add WFET instruction for Armv8.7-a | Przemyslaw Wirkus | 2020-10-28 | 1 | -0/+1 |
| * | aarch64: Add DSB instruction Armv8.7-a variant | Przemyslaw Wirkus | 2020-10-28 | 1 | -0/+5 |
| * | aarch64: Add basic support for armv8.7-a architecture | Przemyslaw Wirkus | 2020-10-28 | 1 | -0/+3 |
| * | aarch64: Add support for Armv8-R DFB alias | Alex Coplan | 2020-09-08 | 1 | -0/+6 |
| * | AArch64: add GAS support for UDF instruction | Alex Coplan | 2020-04-30 | 1 | -0/+3 |
| * | [AArch64, Binutils] Add missing TSB instruction | Sudakshina Das | 2020-04-20 | 1 | -2/+3 |
| * | [AArch64, Binutils] Make hint space instructions valid for Armv8-a | Sudakshina Das | 2020-04-20 | 1 | -30/+17 |
| * | aarch64: Fix MOVPRFX markup for bf16 conversions | Richard Sandiford | 2020-01-31 | 1 | -2/+2 |
| * | AArch64: Fix cfinv disassembly issues | Tamar Christina | 2020-01-27 | 1 | -1/+8 |
| * | Arm64: correct address index operands for LD1RO{H,W,D} | Jan Beulich | 2020-01-03 | 1 | -4/+4 |
| * | Arm64: correct {su,us}dot SIMD encodings | Jan Beulich | 2020-01-03 | 1 | -3/+3 |
| * | Arm64: correct uzp{1,2} mnemonics | Jan Beulich | 2020-01-03 | 1 | -2/+2 |
| * | Arm64: correct 64-bit element fmmla encoding | Jan Beulich | 2020-01-03 | 1 | -1/+1 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2020-01-01 | 1 | -1/+1 |
| * | Arm64: simplify Crypto arch extension handling | Jan Beulich | 2019-12-05 | 1 | -12/+0 |
| * | Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register | Jan Beulich | 2019-11-11 | 1 | -2/+2 |
| * | [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X] | Matthew Malcomson | 2019-11-07 | 1 | -0/+5 |
| * | [binutils][aarch64] Matrix Multiply extension enablement [8/X] | Matthew Malcomson | 2019-11-07 | 1 | -0/+74 |
| * | [binutils][aarch64] Bfloat16 enablement [2/X] | Matthew Malcomson | 2019-11-07 | 1 | -0/+80 |
| * | [gas][aarch64] Armv8.6-a option [1/X] | Matthew Malcomson | 2019-11-07 | 1 | -0/+3 |
| * | Modify the ARNM assembler to accept the omission of the immediate argument fo... | Delia Burduv | 2019-10-30 | 1 | -1/+1 |
| * | [AArch64] Allow MOVPRFX to be used with FMOV | Richard Sandiford | 2019-07-02 | 1 | -1/+1 |
| * | [AArch64] Add missing C_MAX_ELEM flags for SVE conversions | Richard Sandiford | 2019-07-02 | 1 | -28/+28 |
