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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:15:13 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:15:37 +0000 |
| commit | 3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38 (patch) | |
| tree | f8ceee98b93206d0fc7b4180e361dbfa461800b7 /opcodes/aarch64-tbl.h | |
| parent | 01a4d0822025084609380fb989d43bda0667db72 (diff) | |
| download | binutils-gdb-3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38.tar.gz | |
aarch64: [SME] Add SME mode selection and state access instructions
This patch is adding new SME mode selection and state access instructions:
* Add SMSTART and SMSTOP instructions.
* Add SVCR system register.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_sm_za): New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-8-illegal.d: New test.
* testsuite/gas/aarch64/sme-8-illegal.l: New test.
* testsuite/gas/aarch64/sme-8-illegal.s: New test.
* testsuite/gas/aarch64/sme-8.d: New test.
* testsuite/gas/aarch64/sme-8.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_SM_ZA.
(enum aarch64_insn_class): New instruction classes
sme_start and sme_stop.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_pstatefield): New inserter.
(aarch64_ins_sme_sm_za): New inserter.
* aarch64-dis.c (aarch64_ext_imm): New extractor.
(aarch64_ext_pstatefield): New extractor.
(aarch64_ext_sme_sm_za): New extractor.
* aarch64-opc.c (operand_general_constraint_met_p):
New pstatefield value for SME instructions.
(aarch64_print_operand): Printout for OPND_SME_SM_ZA.
(SR_SME): New register SVCR.
* aarch64-opc.h (F_REG_IN_CRM): New register endcoding.
* aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding.
(PSTATE_ENCODE_CRM): Encode CRm field.
(PSTATE_DECODE_CRM): Decode CRm field.
(PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field.
(PSTATE_DECODE_CRM_IMM): Decode CRm immediate field.
(PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate
field.
* aarch64-tbl.h (struct aarch64_opcode): New SMSTART
and SMSTOP instructions.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d74009be3cb..820b082040c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3933,6 +3933,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0), + /* SME instructions (aliases for MSR <sysreg> operations. */ + SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), {}, F_SYS_WRITE, 0), + SME_INSN ("smstop", 0xd503467f, 0xffffffff, sme_stop, 0, OP0 (), {}, F_SYS_WRITE, 0), + SME_INSN ("smstart", 0xd503417f, 0xfffff1ff, sme_start, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), + SME_INSN ("smstop", 0xd503407f, 0xfffff1ff, sme_stop, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), /* System. */ CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), @@ -5765,6 +5770,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ F(FLD_Rn,FLD_imm4_2), \ "memory offset") \ + Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ + F(FLD_CRm), \ + "streaming mode") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ |