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path: root/opcodes/aarch64-tbl.h
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* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-301-0/+11
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-301-0/+1
* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-301-0/+3
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-301-0/+3
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-301-3/+12
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-301-0/+7
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-301-0/+12
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-301-0/+4
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-301-0/+22
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-301-0/+14
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-301-0/+8
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-301-0/+20
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-301-0/+6
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-301-0/+6
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-301-0/+10
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-301-0/+50
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-301-0/+82
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-301-0/+74
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-301-0/+28
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-301-0/+44
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-301-0/+20
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-301-0/+42
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-301-0/+60
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-301-0/+136
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-301-0/+43
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-301-0/+13
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-301-3/+3
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-301-1/+1
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-301-16/+16
* aarch64: Reorder some OP_SVE_* macrosRichard Sandiford2023-03-301-16/+16
* aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford2023-03-301-81/+77
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-301-2/+2
* aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford2023-03-301-21/+18
* aarch64: Treat ZA as a registerRichard Sandiford2023-03-301-1/+1
* aarch64: Make SME instructions use F_STRICTRichard Sandiford2023-03-301-9/+9
* aarch64: Fix PSEL opcode maskRichard Sandiford2023-03-301-1/+1
* aarch64: Add sme-i16i64 and sme-f64f64 aliasesRichard Sandiford2023-03-301-22/+22
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-1/+25
* Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2022-10-171-6/+15
* Arm64: support CLEARBHB aliasJan Beulich2022-10-051-0/+1
* aarch64: Add support for new SME instructionsRichard Sandiford2022-01-061-0/+3
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* aarch64: Add BC instructionRichard Sandiford2021-12-021-0/+7
* aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford2021-12-021-6/+14
* aarch64: Add support for +mopsRichard Sandiford2021-12-021-1/+106
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-171-0/+19
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-171-0/+8
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-171-0/+46
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-171-0/+4
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