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* x86: Don't allow KMOV in TLS code sequencesH.J. Lu2021-11-166-5/+35
* RISC-V: Scalar crypto instruction and entropy source CSR testcases.jiawei2021-11-1641-3/+490
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-0/+29
* Deal with full path in .file 0 directiveEric Botcazou2021-11-158-24/+184
* PowerPC64 @notoc in non-power10 codeAlan Modra2021-11-151-0/+7
* RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu2021-11-114-92/+28
* arm: enable Cortex-A710 CPUPrzemyslaw Wirkus2021-11-104-0/+14
* PR 28447: implement multiple parameters for .file on XCOFFClément Chigot2021-11-106-1/+94
* Modernise yyerrorAlan Modra2021-11-062-5/+7
* RISC-V: Clarify the behavior of .option rvc or norvc.Nelson Chu2021-11-041-21/+18
* asan: dlltool buffer overflow: embedded NUL in stringAlan Modra2021-11-031-3/+1
* ARM: match armeb output for unwind-pacbti-m testAlan Modra2021-11-021-3/+3
* arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2021-11-015-4/+41
* Re: arm: add unwinder encoding support for PACBTIAlan Modra2021-10-293-0/+59
* ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPO...Markus Klein2021-10-284-17/+41
* arm: add unwinder encoding support for PACBTITejas Belagod2021-10-281-5/+57
* RISC-V: Tidy riscv assembler and disassembler.Nelson Chu2021-10-271-288/+304
* x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu2021-10-254-15/+74
* LoongArch gas supportliuzhensong2021-10-2439-5/+4152
* x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu2021-10-227-0/+110
* Re: s12z/disassembler: call memory_error_func when appropriateAlan Modra2021-10-141-1/+2
* RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich2021-10-074-0/+26
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-075-2/+61
* Fix mistake in RX assembler documentation (special section names)Nick Clifton2021-10-011-2/+2
* arm: enable Cortex-R52+ CPUPrzemyslaw Wirkus2021-09-304-0/+12
* aarch64: Enable Cortex-X2 CPUPrzemyslaw Wirkus2021-09-303-2/+9
* aarch64: Enable Cortex-A710 CPUPrzemyslaw Wirkus2021-09-303-1/+8
* aarch64: Enable Cortex-A510 CPUPrzemyslaw Wirkus2021-09-303-0/+9
* aarch64: Update AArch64 features command line options docs 2/2Przemyslaw Wirkus2021-09-301-49/+52
* aarch64: Update AArch64 features command line options docs 1/2Przemyslaw Wirkus2021-09-301-7/+8
* aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus2021-09-303-3/+7
* Add a testcase for PR binutils/27202H.J. Lu2021-09-293-0/+28
* RISC-V: Allow to add numbers in the prefixed extension names.Nelson Chu2021-09-288-9/+14
* x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili2021-09-284-5/+23
* configure: regenerate in all projects that use libtool.m4Nick Alcock2021-09-272-45/+50
* PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner2021-09-256-8/+30
* gas/testsuite/ld-elf/dwarf2-21.d: Pass -WHans-Peter Nilsson2021-09-241-1/+1
* dwarf2 sub-section testAlan Modra2021-09-224-2/+32
* Fix allocate_filenum last dir/file checksAlan Modra2021-09-201-3/+3
* Re: PR28149, debug info with wrong file associationAlan Modra2021-09-201-13/+23
* PR28149 part 2, purge generated line infoAlan Modra2021-09-185-48/+40
* PR28149, debug info with wrong file associationAlan Modra2021-09-188-72/+105
* RISC-V: Merged extension string tables and their version tables into one.Nelson Chu2021-09-171-119/+7
* RISC-V: Update the assembler insn testcase.Nelson Chu2021-09-132-4/+0
* MIPS: don't use get_symbol_name() for section parsing. With s_change_section...Jan Beulich2021-09-132-14/+8
* ia64: don't use get_symbol_name() for section parsing. With cross_section() ...Jan Beulich2021-09-132-12/+9
* Re: gas: Use the directory name in .file 0Alan Modra2021-09-101-18/+18
* gas: Use the directory name in .file 0H.J. Lu2021-09-094-4/+135
* RISC-V: Pretty print values formed with lui and addiw.Jim Wilson2021-09-084-17/+17
* Fix potential use on an uninitialised vairable in the MCore assembler.Nick Clifton2021-09-061-3/+6
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