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| author | jiawei <jiawei@iscas.ac.cn> | 2021-11-15 11:03:42 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-11-16 11:47:55 +0800 |
| commit | 3d1cafa0c60f859940262af7852b21a42dd78ba1 (patch) | |
| tree | b80f2292a60b9442794b600dc6c635adf34236f0 /gas | |
| parent | dfdba097767e42f5163aeb5a97c4aa0084d44457 (diff) | |
| download | binutils-gdb-3d1cafa0c60f859940262af7852b21a42dd78ba1.tar.gz | |
RISC-V: Scalar crypto instructions and operand set.
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from
zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd
and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs'
symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add
a new Entropy Source CSR define 'seed' located at address 0x015.
bfd/
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
crypto extension.
gas/
*config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR.
(riscv_csr_address): Checked for CSR_CLASS_ZKR.
(validate_riscv_insn): Added y and Y for bs and rnum operands.
(riscv_ip): Handle y and Y operands.
include/
* opcode/riscv-opc.h: Added encodings of crypto instructions.
Also defined new csr seed, which address is 0x15.
* opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto.
opcodes/
* riscv-dis.c (print_insn_args): Recognized new y and Y operands.
* riscv-opc.c (riscv_opcodes): Added crypto instructions.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/config/tc-riscv.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 8cea72a9025..8985edf4bfa 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -63,6 +63,7 @@ enum riscv_csr_class CSR_CLASS_I, CSR_CLASS_I_32, /* rv32 only */ CSR_CLASS_F, /* f-ext only */ + CSR_CLASS_ZKR, /* zkr only */ CSR_CLASS_DEBUG /* debug CSR */ }; @@ -875,6 +876,10 @@ riscv_csr_address (const char *csr_name, result = riscv_subset_supports (&riscv_rps_as, "f"); need_check_version = false; break; + case CSR_CLASS_ZKR: + result = riscv_subset_supports (&riscv_rps_as, "zkr"); + need_check_version = false; + break; case CSR_CLASS_DEBUG: need_check_version = false; break; @@ -1085,6 +1090,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'I': break; /* Macro operand, must be constant. */ case 'D': /* RD, floating point. */ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; + case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; case 'Z': /* RS1, CSR number. */ case 'S': /* RS1, floating point. */ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; @@ -2706,6 +2713,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'y': /* bs immediate */ + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if ((unsigned long)imm_expr->X_add_number > 3) + as_bad(_("Improper bs immediate (%lu)"), + (unsigned long)imm_expr->X_add_number); + INSERT_OPERAND(BS, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'Y': /* rnum immediate */ + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if ((unsigned long)imm_expr->X_add_number > 10) + as_bad(_("Improper rnum immediate (%lu)"), + (unsigned long)imm_expr->X_add_number); + INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + case 'z': if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) || imm_expr->X_op != O_constant |