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path: root/arch/riscv/cpu/ax25/Makefile
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* riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang2023-02-171-8/+0
* riscv: ax25: bypass malloc when spl fit boots from ramRick Chen2023-02-011-0/+1
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-261-0/+1
* riscv: Make start.S available for all targetsBin Meng2018-10-031-2/+0
* riscv: cpu: nx25: Rename as ax25Rick Chen2018-05-291-0/+8