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* dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass2023-05-111-1/+1
* riscv: Support CONFIG_REMAKE_ELFSamuel Holland2023-04-201-0/+2
* riscv: Update alignment for some sections in linker scriptsBin Meng2023-04-202-4/+4
* riscv: spl: Remove relocation sectionsBin Meng2023-04-202-25/+2
* riscv: Avoid updating the link registerBin Meng2023-04-201-1/+1
* riscv: Change to use positive offset to access relocation entriesBin Meng2023-04-201-12/+7
* riscv: Optimize loading relocation typeBin Meng2023-04-201-1/+0
* riscv: Optimize source end address calculation in start.SBin Meng2023-04-201-3/+1
* riscv: Enforce DWARF4 outputBin Meng2023-04-201-2/+1
* riscv: Correct a comment in io.hBin Meng2023-04-201-1/+1
* riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang2023-04-206-1/+483
* riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang2023-04-201-0/+99
* riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang2023-04-201-0/+573
* board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang2023-04-201-0/+5
* riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang2023-04-201-0/+28
* riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang2023-04-206-0/+166
* riscv: semihosting: replace inline assembly with assembly fileAndre Przywara2023-03-062-24/+22
* Merge tag 'v2023.04-rc3' into nextTom Rini2023-02-2714-265/+221
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| * riscv: binman: Add help message for missing blobsRick Chen2023-02-171-0/+1
| * riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang2023-02-177-5/+5
| * configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin2023-02-171-0/+1
| * riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin2023-02-171-30/+68
| * riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin2023-02-172-2/+2
| * riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin2023-02-172-37/+43
| * riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang2023-02-172-92/+2
| * riscv: global_data.h: Correct the comment for PLICSWYu Chien Peter Lin2023-02-171-1/+1
* | dm: dts: Convert driver model tags to use new schemaSimon Glass2023-02-147-71/+71
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* Correct SPL uses of LMBSimon Glass2023-02-101-1/+1
* riscv: memcpy: check src and dst before copyRick Chen2023-02-011-0/+2
* riscv: ax25: bypass malloc when spl fit boots from ramRick Chen2023-02-012-0/+28
* riscv: ae350: Enable CCTL_SUENRick Chen2023-02-011-7/+11
* riscv: cpu: check U-Mode before counteren writeNikita Shubin2023-02-011-8/+8
* global: Finish CONFIG -> CFG migrationTom Rini2023-01-201-1/+1
* Merge branch 'next'Tom Rini2023-01-091-2/+0
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| * Convert CONFIG_STANDALONE_LOAD_ADDR to KconfigTom Rini2022-12-221-2/+0
* | efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWAREHeinrich Schuchardt2022-12-291-5/+12
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* arch/riscv: add semihosting support for RISC-VKautuk Consul2022-12-084-0/+52
* riscv: clarify meaning of CONFIG_SBI_V02Heinrich Schuchardt2022-11-151-7/+7
* riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin2022-11-151-3/+11
* riscv: dts: fix the mpfs's reference clock frequencyConor Dooley2022-11-152-8/+10
* riscv: dts: Add QSPI NAND device nodePadmarao Begari2022-11-031-0/+16
* riscv: dts: Update memory configurationPadmarao Begari2022-11-031-58/+17
* riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin2022-11-039-28/+28
* Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass2022-10-311-1/+1
* riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin2022-10-201-3/+4
* riscv: support building double-float modulesHeinrich Schuchardt2022-10-202-3/+27
* riscv: Fix build against binutils 2.38Alexandre Ghiti2022-10-071-1/+10
* dm: core: Drop ofnode_is_available()Simon Glass2022-09-292-2/+2
* treewide: Drop bootm_headers_t typedefSimon Glass2022-09-291-4/+4
* Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...Tom Rini2022-09-266-11/+36
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