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| author | Rick Chen <rick@andestech.com> | 2019-04-02 15:56:42 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-04-08 09:45:08 +0800 |
| commit | dda00ae4ef357233a72c74e6c02d27b70c844422 (patch) | |
| tree | 53f9e29c4d779504b36dbee95bee7f1f44813f4a /arch/riscv | |
| parent | 8848474c5e9093ac27f6b7cc8be156629c7d0bad (diff) | |
| download | u-boot-dda00ae4ef357233a72c74e6c02d27b70c844422.tar.gz | |
riscv: ax25: Andes specific cache shall only support in M-mode
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/ax25/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 68bd4e9419..6b4b92e692 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -14,6 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. |