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| author | Zong Li <zong.li@sifive.com> | 2021-09-01 15:01:43 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-09-07 10:34:29 +0800 |
| commit | 30fa33dc808b8f28185bca9c812225cbc1ec6e8f (patch) | |
| tree | e3986858c31a0d06f2724cbf007aa5d31b245931 /arch/riscv | |
| parent | 835210a125bef56dacb687cb9f4deae61e68e79d (diff) | |
| download | u-boot-30fa33dc808b8f28185bca9c812225cbc1ec6e8f.tar.gz | |
riscv: lib: modify the indent
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ec8fe201d3..874963d731 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ #define _ASM_RISCV_CACHE_H /* cache */ -void cache_flush(void); +void cache_flush(void); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. |