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| author | Peter Hoyes <Peter.Hoyes@arm.com> | 2021-08-19 16:53:10 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-02 10:17:45 -0400 |
| commit | 37a757e227ccfc7d9eef82ab38f8500a832ea01b (patch) | |
| tree | 3d6b9d9d6d0eadf4148449ad067ba0cd5eaac183 /arch/arm/include/asm/system.h | |
| parent | 53b40e8d54fcdb834e10e6538084517524b8401b (diff) | |
| download | u-boot-37a757e227ccfc7d9eef82ab38f8500a832ea01b.tar.gz | |
armv8: Ensure EL1&0 VMSA is enabled
On Armv8-R, the EL1&0 memory system architecture is configurable as a
VMSA or PMSA, and resets to an "architecturally unknown" value.
Add code to armv8_switch_to_el1_m which detects whether the MSA at
EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields.
If it is we must ensure the VMSA is enabled so that a rich OS can boot.
The MSA and MSA_FRAC fields are described in the Armv8-R architecture
profile supplement (section G1.3.7):
https://developer.arm.com/documentation/ddi0600/latest/
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Diffstat (limited to 'arch/arm/include/asm/system.h')
| -rw-r--r-- | arch/arm/include/asm/system.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 77aa18909e..e4c11e830a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -84,6 +84,30 @@ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ /* + * VTCR_EL2 bits definitions + */ +#define VTCR_EL2_MSA (1 << 31) /* EL1&0 memory architecture */ + +/* + * ID_AA64MMFR0_EL1 bits definitions + */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_MASK (0xFUL << 52) /* Memory system + architecture + frac */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_VMSA (0x2UL << 52) /* EL1&0 supports + VMSA */ +#define ID_AA64MMFR0_EL1_MSA_FRAC_PMSA (0x1UL << 52) /* EL1&0 only + supports PMSA*/ +#define ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA (0x0UL << 52) /* No PMSA + support */ +#define ID_AA64MMFR0_EL1_MSA_MASK (0xFUL << 48) /* Memory system + architecture */ +#define ID_AA64MMFR0_EL1_MSA_USE_FRAC (0xFUL << 48) /* Use MSA_FRAC */ +#define ID_AA64MMFR0_EL1_MSA_VMSA (0x0UL << 48) /* Memory system + architecture + is VMSA */ + +/* * ID_AA64ISAR1_EL1 bits definitions */ #define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic |