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* doc: README.socfpga: Update for U-boot 2021.07rel_socfpga_v2021.07_22.08.02_prrel_socfpga_v2021.07_22.08.01_prrel_socfpga_v2021.07_22.07.02_prrel_socfpga_v2021.07_22.07.01_prrel_socfpga_v2021.07_22.06.02_prrel_socfpga_v2021.07_22.06.01_prrel_socfpga_v2021.07_22.05.02_prrel_socfpga_v2021.07_22.05.01_prrel_socfpga_v2021.07_22.04.02_prrel_socfpga_v2021.07_22.04.01_prrel_socfpga_v2021.07_22.03.02_prrel_socfpga_v2021.07_22.03.01_prsocfpga_v2021.07Yau Wai Gan2022-03-011-21/+54
* HSD #15010294106: spl: fit: nand: fix fit loading on bad blocksrel_socfpga_v2021.07_22.02.02_prrel_socfpga_v2021.07_22.02.01_prrel_socfpga_v2021.07_22.01.03_prrel_socfpga_v2021.07_22.01.02_prrel_socfpga_v2021.07_22.01.01_prrel_socfpga_v2021.07_21.12.03_prrel_socfpga_v2021.07_21.12.02_prrel_socfpga_v2021.07_21.12.01_prrel_socfpga_v2021.07_21.11.03_prQPDS21.4_REL_GSRD_PRTien Fong Chee2021-12-022-12/+38
* HSD #1509758009-3: Enable I2C as default for Arria 10 defconfigTien Fong Chee2021-12-011-0/+3
* HSD #18017149974: mtd: spi-nor-ids: add Macronix flash entryTien Fong Chee2021-12-011-0/+2
* mtd: spi-nor-ids: Add SECT_4K to mt25qu512aKris Chaplin2021-12-011-1/+1
* mtd: spi-nor-ids: Add is25lp512 and is25wp512 devicesKris Chaplin2021-12-011-0/+4
* HSD #15010208928: arm: socfpga: a10: Enable double peripheral RBF configQPDS21.3_REL_GSRD_PRQPDS21.1STD_REL_GSRD_PRTien Fong Chee2021-11-165-1/+55
* HSD #14014983936-2: arm: dts: socfpga: Remove kernel and u-boot scriptYau Wai Gan2021-11-123-23/+7
* HSD #14014983936-1: arm: dts: socfpga: Update u-boot binman nodeYau Wai Gan2021-11-123-11/+80
* HSD #14014983937: include: configs: socfpga: Add environment variables for di...Yau Wai Gan2021-11-121-1/+80
* HSD #14014983933-3: configs: socfpga: Combine defconfig for all boot flashesYau Wai Gan2021-11-123-0/+283
* HSD #14014983933-2: configs: socfpga: Remove atf defconfigYau Wai Gan2021-11-127-605/+0
* HSD #14014983933-1: configs: socfpga: Rename the non-atf defconfig to legacyYau Wai Gan2021-11-127-0/+0
* HSD #1509758009-2: i2c: designware_i2c: Remove clk disabled codesTien Fong Chee2021-11-121-5/+0
* HSD #1509758009-1: arm: dts: a10: Correct i2c scl falling timeTien Fong Chee2021-11-122-2/+8
* HSD #14014983934-4: arm: socfpga: soc64: Load and boot for NAND flash with UB...rel_socfpga_v2021.07_RC_21.11.02_prsocfpga_v2021.07_RCSin Hui Kho2021-10-231-5/+5
* HSD #14014983934-3: arm: dts: Update NAND MTD partition for Agilex and Strati...Sin Hui Kho2021-10-232-40/+4
* HSD #14014983934-2: configs: defconfig: Update default NAND MTD partition for...Sin Hui Kho2021-10-234-4/+4
* HSD #14014983934-1: configs: defconfig: Enable UBI and UBIFS for Agilex and S...Sin Hui Kho2021-10-234-4/+32
* arm: socfpga: Export Board ID as U-boot Environment Variablerel_socfpga_v2021.07_RC_21.11.01_prrel_socfpga_v2021.07_RC_21.10.03_prYau Wai Gan2021-10-051-0/+7
* arm: socfpga: Enable U-boot FIT Config Name Match with Board IDYau Wai Gan2021-10-051-5/+8
* arm: socfpga: Add function to get Board IDYau Wai Gan2021-10-052-0/+39
* HSD #1509353019: rsu: Ensure buffer 'flash0_string' not overflowrel_socfpga_v2021.07_RC_21.10.02_prSin Hui Kho2021-09-281-1/+1
* HSD# 14014664649: arm: socfpga: n6010: add PLL initialization for Zarlink chip.Matthew Gerlach2021-09-202-1/+346
* HSD# 14014664649: arm: socfpga: n6010: add PLL data for Zarlink chipMatthew Gerlach2021-09-203-0/+394
* HSD# 14014664649: arm: socfpga: n6010: set bits-per-word for SPI deviceMatthew Gerlach2021-09-201-0/+1
* HSD# 14014664649: spi: designware: add support for bits-per-word DT bindingMatthew Gerlach2021-09-201-2/+14
* HSD #14015124126: arm: socfpga: add configuration for n6010 boardrel_socfpga_v2021.07_RC_21.10.01_prMatthew Gerlach2021-09-172-0/+90
* HSD #14015124126: arm: socfpga: add support for n6010 boardMatthew Gerlach2021-09-174-0/+86
* HSD #14015124126: arm: socfpga: add device tree for n6010 boardMatthew Gerlach2021-09-173-0/+149
* HSD #14015124126: arm: spl: socfpga: add support for booting directly from RAMMatthew Gerlach2021-09-171-2/+12
* HSD #1509829545-2: include: configs: soc64: Update source command formatrel_socfpga_v2021.07_RC_21.09.02_prrel_socfpga_v2021.07_RC_21.09.01_prYau Wai Gan2021-08-271-1/+1
* HSD #1509829545-1: arm: dts: soc64: Add U-boot script in FIT ImageYau Wai Gan2021-08-271-0/+23
* HSD #22011135953-5: arm: socfpga: Enhance checking on potential overwriteTien Fong Chee2021-08-121-3/+4
* drivers: watchdog: wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTARTTeresa Remmet2021-08-021-1/+1
* Revert arm: cp15: update DACR value to activate access controlYau Wai Gan2021-08-021-5/+2
* ddr: altera: n5x: Include DDR4 for the same hardcoding settingsTien Fong Chee2021-07-291-15/+12
* HSD #14014453708: intialize rsu for each commandRadu Bacrau2021-07-291-188/+123
* command: Fix SMC and HVC maximum number of argumentsSiew Chin Lim2021-07-291-3/+3
* Revert "socfpga64: Do not define CONFIG_SYS_MEM_RESERVE_SECURE to 0"Yau Wai Gan2021-07-291-0/+1
* include: configs: soc64: Disable SPL load U-Boot image using raw methodSin Hui Kho2021-07-291-3/+0
* arm: socfpga: soc64: Add support for board_boot_order()Sin Hui Kho2021-07-291-0/+93
* arm: dts: socfpga: soc64: Enable spl-boot-order Property in Device TreeSin Hui Kho2021-07-2911-43/+15
* arm: dts: socfpga: soc64: Consolidate SPL device treesSin Hui Kho2021-07-295-10/+8
* configs: socfpga: soc64: Disable CONFIG_SPL_RAW_IMAGE_SUPPORTSin Hui Kho2021-07-2916-0/+16
* ddr: altera: n5x: Fixing debug log typoTien Fong Chee2021-07-291-6/+6
* HSD #22011135953-4: arm: socfpga: Switch FW settings from codes to DTSTien Fong Chee2021-07-2913-160/+20
* HSD #22011135953-3: arm: dts: socfpga: Copy existing FW & SEC config to DTSTien Fong Chee2021-07-294-2/+151
* HSD #22011135953-2: misc: socfpga_secreg: Enable register settings in DTSTien Fong Chee2021-07-293-0/+97
* HSD #22011135953-1: doc: dtbinding: Add doc for privilege regs settingsTien Fong Chee2021-07-291-0/+26
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