From e870a2ee57e102de19f9f0283033b3336a54f8a3 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Mon, 27 Feb 2023 17:19:21 +0800 Subject: HSD #15012954777-1: arm: socfpga: soc64: Disable F2S bridge Wrong register and value were used to disable the F2S bridge, so this fix ensure the correct register and value to disable F2S bridge. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/reset_manager_s10.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c3047cb3fb..246fb4fe21 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2023 Intel Corporation * */ @@ -168,8 +168,8 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable, RSTMGR_HDSKREQ_FPGAHSREQ); POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKACK), timeout_ms); - clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); __socfpga_udelay(1); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, -- cgit v1.2.1