blob: 7797238e7c5cfff62ecf4867894b6e44d634fe33 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright Altera Corporation (C) 2020. All rights reserved.
*
* Copyright (C) 2022 Intel Corporation
*/
#include "socfpga_stratix10_socdk-u-boot.dtsi"
/ {
memory {
#address-cells = <2>;
#size-cells = <2>;
device_type = "memory";
/*
* Recommended Aliasing addresses
*
* 16GB
* <0 0x00000000 0 0x80000000>,
* <0x10 0x80000000 3 0x80000000>;
*
* 8GB
* <0 0x00000000 0 0x80000000>,
* <0x10 0x80000000 1 0x80000000>;
*
* 4GB
* <0 0x00000000 0 0x80000000>,
* <0x10 0x80000000 0 0x80000000>;
*
* 2GB
* <0 0x00000000 0 0x80000000>;
*
* Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig
* Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size
*/
reg = <0 0x00000000 0 0x80000000>,
<0x10 0x80000000 0 0x80000000>;
u-boot,dm-pre-reloc;
};
soc {
eccmgr {
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
|
