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* BR2975768: Update AMD LWP instructions to match upcoming changesCyrill Gorcunov2010-03-251-8/+9
* insns.dat: in 64-bit mode, accept "monitor rax,ecx,edx".H. Peter Anvin2010-01-061-0/+1
* BR2924380: Add AMD LWP instructionsCyrill Gorcunov2010-01-031-0/+20
* BR2924383: fix XOP instructionsCyrill Gorcunov2010-01-031-4/+10
* BR2924583: fix FMA4 instructionsCyrill Gorcunov2010-01-031-2/+2
* insns.dat: Restore default size of memory operandsCyrill Gorcunov2009-12-161-22/+22
* insns.dat: AVX -- no need for IF_ARx in templateCyrill Gorcunov2009-12-031-12/+12
* insns.dat: remove non-DREX SSE5 instructionsH. Peter Anvin2009-11-091-31/+0
* SSE5: remove all DREX-based instructionsH. Peter Anvin2009-11-091-275/+1
* MOVD xmmreg: not valid with REX.WH. Peter Anvin2009-11-061-4/+4
* IMUL: sbyteX fix -- last oneCyrill Gorcunov2009-11-031-3/+3
* IMUL: fix an additional incorrect sbyte useH. Peter Anvin2009-11-031-1/+1
* BR 2887108: fix incorrect sbyte usage in IMULH. Peter Anvin2009-11-031-2/+2
* insns.dat -- convert FMA instructionsCyrill Gorcunov2009-08-071-192/+192
* insns.dat -- convert AVX instructions part2Cyrill Gorcunov2009-08-071-347/+347
* insns.dat -- convert AVX instructions part1Cyrill Gorcunov2009-08-071-281/+281
* insns.dat: operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-18/+18
* insns.dat -- operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-150/+150
* Add copyright notice to insns.datH. Peter Anvin2009-06-281-6/+35
* ndisasm: fix disassembly of JRCXZH. Peter Anvin2009-06-261-1/+1
* insns.dat: reformatH. Peter Anvin2009-06-261-104/+104
* insns.dat: add relaxed forms for XOP/FMA4/CVT16 instructionsH. Peter Anvin2009-06-261-146/+148
* insns: make the MMX version of PINSRW match the SSE/AVX onesH. Peter Anvin2009-06-241-3/+3
* Intel FMA: drop relaxed formsH. Peter Anvin2009-06-241-192/+192
* Fix the PINSR series of instructionsH. Peter Anvin2009-06-241-18/+21
* insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin2009-06-241-4/+2
* insns.dat: collapse relaxed formsH. Peter Anvin2009-06-241-1212/+608
* insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-171-13/+23
* insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-151-0/+199
* BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin2009-03-171-264/+264
* BR 2690688: add missing VFM instructionsH. Peter Anvin2009-03-171-24/+168
* BR 2689316: PEXTRQ requires REX.WH. Peter Anvin2009-03-161-1/+1
* insns.dat: fix VFNM instructions incorrectly spelled as VFMNH. Peter Anvin2009-03-161-48/+48
* Add VPCLMUL instructionsH. Peter Anvin2009-02-231-0/+12
* PCLMUL is apparently targeted for Westmere with the AES stuffH. Peter Anvin2009-02-211-6/+5
* BR 2557903: fix disassembly of a set of SSE MOV* instructionsH. Peter Anvin2009-02-211-6/+6
* BR 2541252: Fix issues in insns.dat, mostly related to LZCNT and POPCNTH. Peter Anvin2009-02-211-10/+10
* BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin2009-02-211-11/+10
* Fix opcode for VADDSUBPS; operands for VBLEND; add SSE for AES opsH. Peter Anvin2009-02-211-14/+14
* FMA instructions won't be in Sandy BridgeH. Peter Anvin2009-02-211-241/+240
* Update the VFMA* instructions per the AVX spec version 5H. Peter Anvin2009-02-181-64/+240
* insns.dat: fix minor formatting anomaliesH. Peter Anvin2009-02-181-3/+3
* BR 2413278: Nonoptimal forms of arithmetic instructions involving AXH. Peter Anvin2008-12-291-0/+24
* The POPCNT instruction does not need sizes on memory operandsH. Peter Anvin2008-11-061-3/+3
* BR 2229703: POPCNT r64,rm64 not POPCNT r64,rm32H. Peter Anvin2008-11-061-1/+1
* The CRC32 instructions can take 66 prefixes as well as F2H. Peter Anvin2008-10-231-5/+5
* BR 2190521: fix the CRC32 opcodesH. Peter Anvin2008-10-231-5/+5
* BR 2187210: Fix PFRCPV and PFRSQRTVH. Peter Anvin2008-10-221-2/+2
* Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin2008-10-081-5/+5
* Add missing IMUL pattern: reg64,imm8H. Peter Anvin2008-10-071-0/+1
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