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| author | Cyrill Gorcunov <gorcunov@gmail.com> | 2010-03-25 00:37:09 +0300 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2010-03-25 00:37:26 +0300 |
| commit | 1f6a046d8545d232f6dce2493da63e7f0d69e496 (patch) | |
| tree | f83eee57d1a610eb1a686cfdd9eaf72061c580f9 /insns.dat | |
| parent | 0d268fb78cc17360d4b20c6bdd4b54c8c996fc63 (diff) | |
| download | nasm-1f6a046d8545d232f6dce2493da63e7f0d69e496.tar.gz | |
BR2975768: Update AMD LWP instructions to match upcoming changes
The former changes have been committed to binutils.
From initial message:
|
| 2010-03-22 Quentin Neill <quentin.neill@amd.com>
| Sebastian Pop <sebastian.pop@amd.com>
|
| opcodes/
| * i386-dis.c (OP_LWP_I): Removed.
| (reg_table): Do not use OP_LWP_I, use Iq.
| (OP_LWPCB_E): Remove use of names16.
| (OP_LWP_E): Same.
| * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
| should not set the Vex.length bit.
| * i386-tbl.h: Regenerated.
|
| gas/
| * testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns.
| * testsuite/gas/i386/lwp.s: Same.
| * testsuite/gas/i386/x86-64-lwp.d: Updated.
| * testsuite/gas/i386/lwp.d: Updated.
|
So there is no 16 bit instructions anymore.
Also xop.l field should be set to 0.
Based on patch from nasm64developer
Reported-by: nasm64developer
Signed-off-by: nasm64developer
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'insns.dat')
| -rw-r--r-- | insns.dat | 17 |
1 files changed, 9 insertions, 8 deletions
@@ -2814,20 +2814,21 @@ XSHA256 void \336\3\x0F\xA6\xD0 PENT,CYRIX ; ; based on pub number 43724 revision 3.04 date August 2009 ; -LLWPCB reg16 [m: xop.m9.w0.l0.p0 12 /0] AMD -LLWPCB reg32 [m: xop.m9.w0.l1.p0 12 /0] AMD,386 +; updated to match draft from AMD developer (patch has been +; sent to binutils +; 2010-03-22 Quentin Neill <quentin.neill@amd.com> +; Sebastian Pop <sebastian.pop@amd.com> +; +LLWPCB reg32 [m: xop.m9.w0.l0.p0 12 /0] AMD,386 LLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /0] AMD,X64 -SLWPCB reg16 [m: xop.m9.w0.l0.p0 12 /1] AMD -SLWPCB reg32 [m: xop.m9.w0.l1.p0 12 /1] AMD,386 +SLWPCB reg32 [m: xop.m9.w0.l0.p0 12 /1] AMD,386 SLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /1] AMD,X64 -LWPVAL reg16,rm32,imm16 [vmi: xop.m10.w0.ndd.l0.p0 12 /1 iw] AMD,386 -LWPVAL reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l1.p0 12 /1 id] AMD,386 +LWPVAL reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l0.p0 12 /1 id] AMD,386 LWPVAL reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /1 id] AMD,X64 -LWPINS reg16,rm32,imm16 [vmi: xop.m10.w0.ndd.l0.p0 12 /0 iw] AMD,386 -LWPINS reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l1.p0 12 /0 id] AMD,386 +LWPINS reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l0.p0 12 /0 id] AMD,386 LWPINS reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /0 id] AMD,X64 ;# AMD XOP, FMA4 and CVT16 instructions (SSE5) |