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and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };
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