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path: root/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
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* util: Move src/gallium/auxiliary/os/os_mman.h to src/util/os_mman.hYonggang Luo2022-11-151-1/+1
* virgl/vtest: implement resource_create_frontItalo Nicola2021-12-111-5/+22
* virgl/vtest: use correct resource stride in flush_frontbufferItalo Nicola2021-12-111-1/+2
* virgl/drm: New optimization for uploading texturesmwezdeck2021-12-081-1/+6
* virgl: Add more meta data to cached resourcesRohan Garg2021-07-271-3/+24
* virgl: add flags to (*resource_create) callbackGurchetan Singh2020-10-011-2/+3
* gallium: rename 'state tracker' to 'frontend'Marek Olšák2020-05-131-1/+1
* virgl: Use align_free for align_malloc allocated bufferSzymon Andrzejuk2020-02-011-1/+1
* util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt2019-11-141-1/+1
* virgl: fix format conversion for recent gallium changes.Dave Airlie2019-08-261-1/+1
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-171-12/+7
* virgl: Use virgl_resource_cache in the vtest winsysAlexandros Frantzis2019-06-141-117/+38
* virgl: Make VIRGL_BIND_STAGING resources cacheableAlexandros Frantzis2019-06-071-1/+2
* virgl: Deduplicate checks for resource cachingAlexandros Frantzis2019-06-071-9/+7
* virgl: Don't try to use cached resources for legacy fencesAlexandros Frantzis2019-06-071-5/+8
* virgl: export resource_is_busy from winsysChia-I Wu2019-05-061-5/+7
* virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh2019-04-181-1/+10
* virgl/vtest: wait after issuing a transfer getGurchetan Singh2019-04-181-2/+3
* virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh2019-04-181-4/+35
* virgl/vtest: receive and handle shared memory fdGurchetan Singh2019-04-181-6/+45
* virgl/vtest: plumb support for shared memoryGurchetan Singh2019-04-181-1/+2
* virgl/vtest: execute a transfer_get when flushing the front bufferGurchetan Singh2019-04-181-22/+21
* virgl: hide fence internals from the driverChia-I Wu2019-04-151-12/+18
* virgl: handle fence_server_sync in winsysChia-I Wu2019-04-151-3/+1
* virgl: use uint16_t mask instead of separate booleansGurchetan Singh2019-03-131-30/+32
* virgl/vtest: deprecate protocol version 1Gurchetan Singh2019-02-271-20/+2
* virgl: make winsys modifications for encoded transfersGurchetan Singh2019-02-151-1/+3
* virgl/vtest: fix front buffer flush with protocol version 0.Dave Airlie2018-12-281-1/+1
* virgl,vtest: Initialize return valueGert Wollny2018-11-281-1/+1
* virgl: fix vtest regression since fencing changes.Dave Airlie2018-11-191-0/+1
* virgl: Clean up fences commitRobert Foss2018-11-181-1/+0
* virgl: native fence fd supportRobert Foss2018-11-161-2/+8
* virgl/vtest-winsys: Use virgl version of bind flagsGert Wollny2018-11-021-1/+1
* virgl: Pass resource size and transfer offsetsTomeu Vizoso2018-10-061-10/+34
* winsys/virgl/vtest: Correct off-by-one error in resource allocationGert Wollny2018-09-051-4/+9
* virgl: resize resource bo allocation if we need to.Dave Airlie2018-03-151-2/+6
* virgl: handle getting new capsets.Dave Airlie2018-03-051-0/+2
* util: move os_time.[ch] to src/utilNicolai Hähnle2017-11-091-1/+1
* gallium/util: replace pipe_mutex_unlock() with mtx_unlock()Timothy Arceri2017-03-071-4/+4
* gallium/util: replace pipe_mutex_lock() with mtx_lock()Timothy Arceri2017-03-071-3/+3
* gallium/util: replace pipe_mutex_destroy() with mtx_destroy()Timothy Arceri2017-03-071-1/+1
* gallium/util: replace pipe_mutex_init() with mtx_init()Timothy Arceri2017-03-071-1/+1
* virgl: fix checking fencesMarc-André Lureau2016-06-091-1/+1
* virgl: wrap ret assignment with braces to do correct thingDave Airlie2015-11-081-1/+1
* gallium/swrast: fixup build breakage and warningsDave Airlie2015-10-311-1/+1
* winsys/virgl: rework line wrapping/indentEmil Velikov2015-10-301-51/+66
* virgl: unwrap the includesEmil Velikov2015-10-301-3/+4
* winsys/virgl: remove calloc/malloc castsEmil Velikov2015-10-301-2/+1
* winsys/virgl: throw in some inline wrappersEmil Velikov2015-10-301-5/+5
* virgl: remove the _FILE_OFFSET_BITS definesEmil Velikov2015-10-301-2/+0
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