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path: root/src/gallium/drivers/r600
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* nir: Drop unused name from nir_ssa_dest_initAlyssa Rosenzweig2023-05-176-21/+20
* treewide: Stop lowering legacy atomicsAlyssa Rosenzweig2023-05-161-1/+0
* r600: Use unified atomicsAlyssa Rosenzweig2023-05-154-134/+61
* r600/sfn: Fix iterator useGert Wollny2023-05-081-1/+1
* radeon: add radeon_info parameter into radeon_winsys::surface_initMarek Olšák2023-05-081-2/+2
* r600/sfn: fix cube to array lowering for LODGert Wollny2023-05-061-1/+1
* r600/sfn: Ass support for image_samplesGert Wollny2023-05-062-0/+38
* r600: remove unused codeThomas H.P. Andersen2023-05-041-24/+0
* r600: fix refcnt imbalance related to atomic_buffer_statePatrick Lerda2023-05-031-0/+10
* r600/sfn: assign window_space_position in shader stateGert Wollny2023-05-011-0/+4
* r600+sfn: Assign ps_conservative_z and switch to NIR definesGert Wollny2023-05-013-6/+11
* r600/sfn: Tie in address load splittingGert Wollny2023-04-283-4/+25
* r600/sfn: prepare for emitting AR loadsGert Wollny2023-04-281-41/+64
* r600/sfn: factor out index loading for non-alu instructionsGert Wollny2023-04-281-30/+28
* r600/sfn: Can't use an indirect array access as source to AR loadGert Wollny2023-04-281-0/+7
* r600/sfn: print failing block when scheduling failsGert Wollny2023-04-281-0/+13
* r600/sfn: Add more tests and update to use address splitsGert Wollny2023-04-282-4/+1
* r600/sfn: scheduled instructions are always readyGert Wollny2023-04-281-0/+2
* r600/sfn: Fix copy-prop with array accessGert Wollny2023-04-282-50/+53
* r600/sfn: Override Array access handling in backend assemblerGert Wollny2023-04-282-0/+75
* r600/sfn: Add handling for R600 indirect access alias handlingGert Wollny2023-04-285-32/+481
* r600/sfn: Add chip family to shader classGert Wollny2023-04-283-3/+57
* r600/sfn: Start a new ALU CF on index use, not on index emissionGert Wollny2023-04-282-7/+50
* r600/sfn: set CF force flag always when starting a new blockGert Wollny2023-04-281-3/+1
* r600/sfn: Add test for multiple index loadGert Wollny2023-04-281-0/+80
* r600/sfn: Don't copy-propagate indirect access into LDS instrGert Wollny2023-04-282-13/+25
* r600/sfn: Add more tests and update to use address splitsGert Wollny2023-04-284-20/+221
* r600/sfn: take address loads into account when schedulingGert Wollny2023-04-282-24/+73
* r600/sfn: Add function to check whether a group loads a index registerGert Wollny2023-04-282-0/+11
* r600/sfn: Add pass to split addess and index register loadsGert Wollny2023-04-285-1/+832
* r600/sfn: Add interface to count AR uses in ALU opGert Wollny2023-04-281-0/+4
* r600/sfn: Add a RW get function of IF predicate accessGert Wollny2023-04-281-0/+1
* r600/sfn: AR and IDX don't need the write flag, but haev a parentGert Wollny2023-04-281-5/+10
* r600/sfn: Be able to track expected AR usesGert Wollny2023-04-281-0/+8
* r600/sfn: Update resource based instruction index mode checkGert Wollny2023-04-281-1/+2
* r600/sfn: Add function to insert op in blockGert Wollny2023-04-282-0/+8
* r600/sfn: add method to update indirect address to all instrution typesGert Wollny2023-04-285-0/+64
* r600/sfn: handle AR and IDX register in shader from stringGert Wollny2023-04-281-1/+3
* r600/sfn: Prepare uniforms and local arrays for better address handlingGert Wollny2023-04-283-9/+50
* r600: Allow both index registers for all CF typesGert Wollny2023-04-281-3/+3
* r600/sfn: don't allow more than one AR per instructionGert Wollny2023-04-281-22/+24
* r600/sfn: Rework query for indirect access in alu instr and optGert Wollny2023-04-285-27/+50
* r600/sfn: Add address and index registers creation to ValueFactoryGert Wollny2023-04-282-6/+54
* r600/sfn/tests: Cleanup and move some code aroundGert Wollny2023-04-283-42/+40
* r600/sfn: Handle MOVA_INT in sfn assemblerGert Wollny2023-04-282-3/+12
* r600/sfn: don't track address registers in live rangesGert Wollny2023-04-281-7/+15
* r600/sfn: Add a type for address registersGert Wollny2023-04-283-3/+49
* radeonsi: stop reporting reset to app once gpu recovery is donePierre-Eric Pelloux-Prayer2023-04-271-1/+1
* r600: remove TGSI code pathGert Wollny2023-04-275-11498/+30
* r600/sfn: make sure f2u32 is lowered late and correctly for 64 bit floatsGert Wollny2023-04-222-2/+5
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