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path: root/src/freedreno/ir3/tests/disasm.c
Commit message (Expand)AuthorAgeFilesLines
* ir3: documents (ss) flag for cat7 instructionsDanylo Piliaiev2023-04-271-0/+1
* ir3/a7xx: Add definitions for (last) src GPR attributeMark Collins2023-04-271-0/+8
* ir3/a7xx: Document "alias" instructionDanylo Piliaiev2023-04-271-0/+5
* ir3: Document that stc has higher DST upper bound than we definedDanylo Piliaiev2023-04-271-0/+3
* ir3/a7xx: Add STSC definitionDanylo Piliaiev2023-04-271-0/+6
* ir3/a7xx: Add new form of stg.a/ldg.a addressingDanylo Piliaiev2023-04-271-0/+6
* ir3/a7xx: Add new lock/unlock CS instructionsDanylo Piliaiev2023-04-271-0/+3
* freedreno: Early exit in device matching if id doesn't have chip_idDanylo Piliaiev2023-04-271-0/+1
* ir3: Add cat7 sleep instructionDanylo Piliaiev2023-02-211-0/+1
* ir3: Add cat5/cat7 cache related instructionsDanylo Piliaiev2023-02-211-0/+4
* ir3, isaspec: add raw instruction to assembler/disassembler.Amber2023-01-261-0/+2
* ir3: Add missing cat5 encoding to asm parserConnor Abbott2022-10-041-0/+1
* ir3: Refactor ir3_compiler_create() to take an options structConnor Abbott2022-03-171-1/+2
* ir3: Implement and document ldc.kConnor Abbott2022-03-171-0/+5
* ir3: Better assemble/disassemble stcConnor Abbott2022-03-171-2/+6
* ir3: New cat3 instructionsDanylo Piliaiev2022-01-101-3/+14
* ir3: Add gen4 new subgroup instructionsDanylo Piliaiev2021-12-071-0/+11
* freedreno/ir3: add a6xx global atomics and separate atomic opcodesDanylo Piliaiev2021-11-231-4/+7
* ir3: print half-dst/src for ldib.b/stib.bDanylo Piliaiev2021-11-221-1/+1
* freedreno: Fix the uniform/nonuniform handling for cat5 bindful modes.Emma Anholt2021-11-101-3/+16
* ir3: Add support for (dis)assembling flat.bMatt Turner2021-11-041-0/+1
* freedreno/ir3/tests: Add some 8/16b ldg/stg testsRob Clark2021-10-191-0/+5
* freedreno/ir3/tests: Don't skip encode test if decode failsRob Clark2021-10-191-1/+0
* freedreno/ir3/tests: Add additional disasm test vectorsRob Clark2021-10-151-0/+3
* freedreno/ir3/tests: Fix indentationRob Clark2021-10-151-147/+147
* ir3: Fix handling cat6 immediatesConnor Abbott2021-10-121-14/+8
* ir3: support source modes for resinfo.bDanylo Piliaiev2021-10-071-0/+2
* freedreno/ir3: Add encode/decode support for a5xx's LDIB.Emma Anholt2021-09-031-3/+14
* freedreno/all: Introduce fd_dev_idRob Clark2021-08-061-1/+3
* ir3: Reformat source with clang-formatConnor Abbott2021-07-121-122/+127
* ir3: Manually reformat some placesConnor Abbott2021-07-121-144/+148
* ir3: add newly found shlg.b16 instructionDanylo Piliaiev2021-07-091-0/+3
* ir3: add ldg.a,stg.a which allow complex in-place offset calculationDanylo Piliaiev2021-06-251-6/+16
* ir3: Assemble and disassemble swz/gat/sctConnor Abbott2021-04-191-0/+5
* ir3, tu: Add compiler flag for robust UBO behaviorConnor Abbott2021-04-151-1/+1
* turnip: enable VK_KHR_16bit_storage on A650Danylo Piliaiev2021-04-011-0/+1
* ir3/isa: account for randomly set by blob lowest bit of ibo atomicsDanylo Piliaiev2021-03-311-4/+4
* ir3/isa,parser: fix encoding and parsing of bindless s2en SAMDanylo Piliaiev2021-03-171-0/+1
* ir3: Add nonuniform encodings to ir3 encoder and parserHyunjun Ko2021-03-171-0/+11
* ir3: use OPC_GETBUF to get size of sampler buffersDanylo Piliaiev2021-03-101-0/+2
* freedreno/ir3/parser: add cat7 supportDanylo Piliaiev2021-01-151-0/+7
* freedreno/ir3: Small resinfo disasm tweakRob Clark2021-01-131-5/+5
* freedreno/ir3/tests: Switch disasm test over to new decoderRob Clark2021-01-131-13/+13
* freedreno/ir3: Fix ldg decoding/parsingRob Clark2021-01-131-0/+5
* freedreno/ir3/parser: Fix pre-a6xx stib parsingRob Clark2021-01-061-1/+1
* freedreno/ir3/parser: a6xx ldib/stib parsingRob Clark2021-01-061-2/+11
* freedreno/ir3: Fix pre-a6xx ldgb/stib parsingRob Clark2021-01-061-0/+3
* freedreno/ir3: Explicitly flag disasm test vectors that don't parseRob Clark2021-01-061-9/+27
* freedreno/ir3: Fix ldg decoding/parsingRob Clark2021-01-061-0/+6
* freedreno/ir3/parser: Fixup stg parsing and add more testsRob Clark2021-01-061-0/+4