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-rw-r--r--src/mesa/drivers/dri/intel/intel_chipset.h4
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c25
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h1
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c13
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.h3
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c7
-rw-r--r--src/mesa/drivers/dri/intel/intel_pixel_draw.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.h2
9 files changed, 36 insertions, 29 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index a0b22669253..dbc08c872b9 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -93,7 +93,7 @@
#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
-#define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid))
+#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \
@@ -118,7 +118,7 @@
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
- IS_IGDNG(devid) || \
+ IS_GEN5(devid) || \
IS_GEN6(devid))
#define IS_9XX(devid) (IS_915(devid) || \
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index daafe41a902..365b82113b7 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -159,10 +159,10 @@ intelGetString(GLcontext * ctx, GLenum name)
chipset = "Intel(R) B43";
break;
case PCI_CHIP_ILD_G:
- chipset = "Intel(R) IGDNG_D";
+ chipset = "Intel(R) Ironlake Desktop";
break;
case PCI_CHIP_ILM_G:
- chipset = "Intel(R) IGDNG_M";
+ chipset = "Intel(R) Ironlake Mobile";
break;
default:
chipset = "Unknown Intel Chipset";
@@ -362,7 +362,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
if (buffers[i].attachment == __DRI_BUFFER_DEPTH)
depth_region = region;
- intel_renderbuffer_set_region(rb, region);
+ intel_renderbuffer_set_region(intel, rb, region);
intel_region_release(&region);
if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
@@ -374,7 +374,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
continue;
intel_region_reference(&stencil_region, region);
- intel_renderbuffer_set_region(rb, stencil_region);
+ intel_renderbuffer_set_region(intel, rb, stencil_region);
intel_region_release(&stencil_region);
}
}
@@ -615,8 +615,16 @@ intelInitContext(struct intel_context *intel,
intel->gen = 6;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
+ } else if (IS_GEN5(intel->intelScreen->deviceID)) {
+ intel->gen = 5;
+ intel->needs_ff_sync = GL_TRUE;
+ intel->has_luminance_srgb = GL_TRUE;
} else if (IS_965(intel->intelScreen->deviceID)) {
intel->gen = 4;
+ if (IS_G4X(intel->intelScreen->deviceID)) {
+ intel->has_luminance_srgb = GL_TRUE;
+ intel->is_g4x = GL_TRUE;
+ }
} else if (IS_9XX(intel->intelScreen->deviceID)) {
intel->gen = 3;
if (IS_945(intel->intelScreen->deviceID)) {
@@ -626,15 +634,6 @@ intelInitContext(struct intel_context *intel,
intel->gen = 2;
}
- if (IS_IGDNG(intel->intelScreen->deviceID)) {
- intel->is_ironlake = GL_TRUE;
- intel->needs_ff_sync = GL_TRUE;
- intel->has_luminance_srgb = GL_TRUE;
- } else if (IS_G4X(intel->intelScreen->deviceID)) {
- intel->has_luminance_srgb = GL_TRUE;
- intel->is_g4x = GL_TRUE;
- }
-
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
intel->driScreen->myNum,
(intel->gen >= 4) ? "i965" : "i915");
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 0fd8acc201b..fb087c036c8 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -142,7 +142,6 @@ struct intel_context
*/
int gen;
GLboolean needs_ff_sync;
- GLboolean is_ironlake;
GLboolean is_g4x;
GLboolean is_945;
GLboolean has_luminance_srgb;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index ba3bb8fdba4..8ae0b9cdb57 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -42,7 +42,9 @@
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
#include "intel_regions.h"
-
+#ifndef I915
+#include "brw_state.h"
+#endif
#define FILE_DEBUG_FLAG DEBUG_FBO
@@ -280,7 +282,8 @@ intel_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
void
-intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
+intel_renderbuffer_set_region(struct intel_context *intel,
+ struct intel_renderbuffer *rb,
struct intel_region *region)
{
struct intel_region *old;
@@ -288,6 +291,12 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
old = rb->region;
rb->region = NULL;
intel_region_reference(&rb->region, region);
+#ifndef I915
+ if (old) {
+ brw_state_cache_bo_delete(&brw_context(&intel->ctx)->surface_cache,
+ old->buffer);
+ }
+#endif
intel_region_release(&old);
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 72413f73694..028f657d12d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -82,7 +82,8 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, int attIndex)
extern void
-intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
+intel_renderbuffer_set_region(struct intel_context *intel,
+ struct intel_renderbuffer *irb,
struct intel_region *region);
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 5b6b4b26240..0483ea4aa7d 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -117,17 +117,16 @@ intel_miptree_create(struct intel_context *intel,
GLboolean expect_accelerated_upload)
{
struct intel_mipmap_tree *mt;
- uint32_t tiling;
+ uint32_t tiling = I915_TILING_NONE;
if (intel->use_texture_tiling && compress_byte == 0) {
if (intel->gen >= 4 &&
(base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT))
tiling = I915_TILING_Y;
- else
+ else if (width0 >= 64)
tiling = I915_TILING_X;
- } else
- tiling = I915_TILING_NONE;
+ }
mt = intel_miptree_create_internal(intel, target, internal_format,
first_level, last_level, width0,
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index bd1dd13fb7d..a40b232fff8 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -167,7 +167,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
irb = intel_create_renderbuffer(MESA_FORMAT_ARGB8888);
irb->Base.Width = depth_irb->Base.Width;
irb->Base.Height = depth_irb->Base.Height;
- intel_renderbuffer_set_region(irb, depth_irb->region);
+ intel_renderbuffer_set_region(intel, irb, depth_irb->region);
/* Create a name for our renderbuffer, which lets us use other mesa
* rb functions for convenience.
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 7d69ea4484a..cdca8de00a7 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -63,9 +63,9 @@ void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *
}
}
-void i945_miptree_layout_2d( struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- uint32_t tiling )
+void i945_miptree_layout_2d(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ uint32_t tiling, int nr_images)
{
GLuint align_h = 2, align_w = 4;
GLuint level;
@@ -111,7 +111,7 @@ void i945_miptree_layout_2d( struct intel_context *intel,
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
GLuint img_height;
- intel_miptree_set_level_info(mt, level, 1, x, y, width,
+ intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
height, 1);
if (mt->compressed)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index a9ac9e7eb48..1c8c53e5459 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -40,5 +40,5 @@ static INLINE GLuint minify( GLuint d )
extern void i945_miptree_layout_2d(struct intel_context *intel,
struct intel_mipmap_tree *mt,
- uint32_t tiling);
+ uint32_t tiling, int nr_images);
extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *);
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