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Diffstat (limited to 'src/amd/vulkan/radv_shader.c')
-rw-r--r--src/amd/vulkan/radv_shader.c131
1 files changed, 92 insertions, 39 deletions
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 98abe8cd437..2bd4c351745 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -48,9 +48,11 @@
#include "util/debug.h"
#include "ac_exp_param.h"
+#include "aco_interface.h"
+
#include "util/string_buffer.h"
-static const struct nir_shader_compiler_options nir_options = {
+static const struct nir_shader_compiler_options nir_options_llvm = {
.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp16 = true,
@@ -80,6 +82,36 @@ static const struct nir_shader_compiler_options nir_options = {
.use_interpolated_input_intrinsics = true,
};
+static const struct nir_shader_compiler_options nir_options_aco = {
+ .vertex_id_zero_based = true,
+ .lower_scmp = true,
+ .lower_flrp16 = true,
+ .lower_flrp32 = true,
+ .lower_flrp64 = true,
+ .lower_device_index_to_zero = true,
+ .lower_fdiv = true,
+ .lower_bitfield_insert_to_bitfield_select = true,
+ .lower_bitfield_extract = true,
+ .lower_sub = true, /* TODO: set this to false once !1236 is merged */
+ .lower_pack_snorm_2x16 = true,
+ .lower_pack_snorm_4x8 = true,
+ .lower_pack_unorm_2x16 = true,
+ .lower_pack_unorm_4x8 = true,
+ .lower_unpack_snorm_2x16 = true,
+ .lower_unpack_snorm_4x8 = true,
+ .lower_unpack_unorm_2x16 = true,
+ .lower_unpack_unorm_4x8 = true,
+ .lower_unpack_half_2x16 = true,
+ .lower_extract_byte = true,
+ .lower_extract_word = true,
+ .lower_ffma = true,
+ .lower_fpow = true,
+ .lower_mul_2x32_64 = true,
+ .lower_rotate = true,
+ .max_unroll_iterations = 32,
+ .use_interpolated_input_intrinsics = true,
+};
+
bool
radv_can_dump_shader(struct radv_device *device,
struct radv_shader_module *module,
@@ -257,15 +289,18 @@ radv_shader_compile_to_nir(struct radv_device *device,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
- const struct radv_pipeline_layout *layout)
+ const struct radv_pipeline_layout *layout,
+ bool use_aco)
{
nir_shader *nir;
+ const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
+ &nir_options_llvm;
if (module->nir) {
/* Some things such as our meta clear/blit code will give us a NIR
* shader directly. In that case, we just ignore the SPIR-V entirely
* and just use the NIR shader */
nir = module->nir;
- nir->options = &nir_options;
+ nir->options = nir_options;
nir_validate_shader(nir, "in internal shader");
assert(exec_list_length(&nir->functions) == 1);
@@ -305,13 +340,13 @@ radv_shader_compile_to_nir(struct radv_device *device,
.descriptor_indexing = true,
.device_group = true,
.draw_parameters = true,
- .float16 = true,
+ .float16 = !device->physical_device->use_aco,
.float64 = true,
.geometry_streams = true,
.image_read_without_format = true,
.image_write_without_format = true,
- .int8 = true,
- .int16 = true,
+ .int8 = !device->physical_device->use_aco,
+ .int16 = !device->physical_device->use_aco,
.int64 = true,
.int64_atomics = true,
.multiview = true,
@@ -320,8 +355,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
.runtime_descriptor_array = true,
.shader_viewport_index_layer = true,
.stencil_export = true,
- .storage_8bit = true,
- .storage_16bit = true,
+ .storage_8bit = !device->physical_device->use_aco,
+ .storage_16bit = !device->physical_device->use_aco,
.storage_image_ms = true,
.subgroup_arithmetic = true,
.subgroup_ballot = true,
@@ -343,7 +378,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir = spirv_to_nir(spirv, module->size / 4,
spec_entries, num_spec_entries,
stage, entrypoint_name,
- &spirv_options, &nir_options);
+ &spirv_options, nir_options);
assert(nir->info.stage == stage);
nir_validate_shader(nir, "after spirv_to_nir");
@@ -383,6 +418,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_split_per_member_structs);
+ if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
+ NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
if (nir->info.stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_input_attachments, true);
@@ -961,7 +998,7 @@ radv_shader_variant_create(struct radv_device *device,
assert(binary->type == RADV_BINARY_TYPE_LEGACY);
config = ((struct radv_shader_binary_legacy *)binary)->config;
variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
- variant->exec_size = variant->code_size;
+ variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
}
variant->info = binary->info;
@@ -1049,13 +1086,12 @@ shader_variant_compile(struct radv_device *device,
struct radv_nir_compiler_options *options,
bool gs_copy_shader,
bool keep_shader_info,
+ bool use_aco,
struct radv_shader_binary **binary_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
- enum ac_target_machine_options tm_options = 0;
- struct ac_llvm_compiler ac_llvm;
struct radv_shader_binary *binary = NULL;
- bool thread_compiler;
+ bool init_llvm;
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
@@ -1079,32 +1115,48 @@ shader_variant_compile(struct radv_device *device,
else
options->wave_size = device->physical_device->ge_wave_size;
- if (options->supports_spill)
- tm_options |= AC_TM_SUPPORTS_SPILL;
- if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
- tm_options |= AC_TM_SISCHED;
- if (options->check_ir)
- tm_options |= AC_TM_CHECK_IR;
- if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
- tm_options |= AC_TM_NO_LOAD_STORE_OPT;
-
- thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
- ac_init_llvm_once();
- radv_init_llvm_compiler(&ac_llvm,
- thread_compiler,
- chip_family, tm_options,
- options->wave_size);
- if (gs_copy_shader) {
- assert(shader_count == 1);
- radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
- info, options);
+ init_llvm = !use_aco || options->dump_shader;
+#ifndef NDEBUG
+ init_llvm |= options->record_llvm_ir;
+#endif
+ if (init_llvm)
+ ac_init_llvm_once();
+
+ if (use_aco) {
+ aco_compile_shader(shader_count, shaders, &binary, info, options);
+ binary->info = *info;
} else {
- radv_compile_nir_shader(&ac_llvm, &binary, info,
- shaders, shader_count, options);
- }
- binary->info = *info;
+ enum ac_target_machine_options tm_options = 0;
+ struct ac_llvm_compiler ac_llvm;
+ bool thread_compiler;
+
+ if (options->supports_spill)
+ tm_options |= AC_TM_SUPPORTS_SPILL;
+ if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+ tm_options |= AC_TM_SISCHED;
+ if (options->check_ir)
+ tm_options |= AC_TM_CHECK_IR;
+ if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
+ tm_options |= AC_TM_NO_LOAD_STORE_OPT;
+
+ thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
+ radv_init_llvm_compiler(&ac_llvm,
+ thread_compiler,
+ chip_family, tm_options,
+ options->wave_size);
+
+ if (gs_copy_shader) {
+ assert(shader_count == 1);
+ radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
+ info, options);
+ } else {
+ radv_compile_nir_shader(&ac_llvm, &binary, info,
+ shaders, shader_count, options);
+ }
- radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
+ binary->info = *info;
+ radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
+ }
struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
keep_shader_info);
@@ -1143,6 +1195,7 @@ radv_shader_variant_compile(struct radv_device *device,
const struct radv_shader_variant_key *key,
struct radv_shader_info *info,
bool keep_shader_info,
+ bool use_aco,
struct radv_shader_binary **binary_out)
{
struct radv_nir_compiler_options options = {0};
@@ -1156,7 +1209,7 @@ radv_shader_variant_compile(struct radv_device *device,
options.robust_buffer_access = device->robust_buffer_access;
return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
- &options, false, keep_shader_info, binary_out);
+ &options, false, keep_shader_info, use_aco, binary_out);
}
struct radv_shader_variant *
@@ -1172,7 +1225,7 @@ radv_create_gs_copy_shader(struct radv_device *device,
options.key.has_multiview_view_index = multiview;
return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
- info, &options, true, keep_shader_info, binary_out);
+ info, &options, true, keep_shader_info, false, binary_out);
}
void
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