diff options
-rw-r--r-- | src/panfrost/midgard/midgard_compile.c | 3 | ||||
-rw-r--r-- | src/panfrost/midgard/midgard_nir_lower_image_bitsize.c | 12 |
2 files changed, 4 insertions, 11 deletions
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 6afd78c19ce..80795a1de98 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -395,6 +395,8 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id) if (quirks & MIDGARD_BROKEN_LOD) NIR_PASS_V(nir, midgard_nir_lod_errata); + NIR_PASS_V(nir, nir_lower_legacy_atomics); + /* Midgard image ops coordinates are 16-bit instead of 32-bit */ NIR_PASS_V(nir, midgard_nir_lower_image_bitsize); @@ -463,7 +465,6 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend) NIR_PASS(progress, nir, nir_copy_prop); NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_lower_legacy_atomics); /* Backend scheduler is purely local, so do some global optimizations * to reduce register pressure. */ diff --git a/src/panfrost/midgard/midgard_nir_lower_image_bitsize.c b/src/panfrost/midgard/midgard_nir_lower_image_bitsize.c index 69c18b9be0c..89f611b44cd 100644 --- a/src/panfrost/midgard/midgard_nir_lower_image_bitsize.c +++ b/src/panfrost/midgard/midgard_nir_lower_image_bitsize.c @@ -39,16 +39,8 @@ nir_lower_image_bitsize(nir_builder *b, nir_instr *instr, UNUSED void *data) switch (intr->intrinsic) { case nir_intrinsic_image_load: case nir_intrinsic_image_store: - case nir_intrinsic_image_atomic_add: - case nir_intrinsic_image_atomic_and: - case nir_intrinsic_image_atomic_comp_swap: - case nir_intrinsic_image_atomic_exchange: - case nir_intrinsic_image_atomic_imax: - case nir_intrinsic_image_atomic_imin: - case nir_intrinsic_image_atomic_or: - case nir_intrinsic_image_atomic_umax: - case nir_intrinsic_image_atomic_umin: - case nir_intrinsic_image_atomic_xor: + case nir_intrinsic_image_atomic: + case nir_intrinsic_image_atomic_swap: break; default: return false; |