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| author | Marek Olšák <marek.olsak@amd.com> | 2021-11-16 19:42:07 -0500 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2021-11-20 00:03:45 +0000 |
| commit | f96d1757bba86d20bbca649d1027ba4ac07268a0 (patch) | |
| tree | f25f4091f6c019e0cd6ec46a817e644e3c7c4bd8 /src | |
| parent | 2418da2d4afe5534ae1bc44a24054d43cf9de0a5 (diff) | |
| download | mesa-f96d1757bba86d20bbca649d1027ba4ac07268a0.tar.gz | |
radeonsi: restructure code that declares merged VS-GS and TES-GS SGPRs
no change in the SGPR layout
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 51807271d32..c9df3cca914 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -533,27 +533,26 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) ctx, (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL)); } - if (ctx->stage == MESA_SHADER_VERTEX) { - if (shader->selector->info.base.vs.blit_sgprs_amd) { - declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd); - } else { - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits); - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.base_vertex); - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.draw_id); - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.start_instance); - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->small_prim_cull_info); - declare_vb_descriptor_input_sgprs(ctx); - } + if (ctx->stage == MESA_SHADER_VERTEX && shader->selector->info.base.vs.blit_sgprs_amd) { + declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd); } else { - /* TES or GS */ ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits); - if (ctx->stage == MESA_SHADER_TESS_EVAL) { + if (ctx->stage == MESA_SHADER_VERTEX) { + ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.base_vertex); + ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.draw_id); + ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.start_instance); + } else if (ctx->stage == MESA_SHADER_TESS_EVAL) { ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tes_offchip_addr); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */ - ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->small_prim_cull_info); } + + if (ctx->stage != MESA_SHADER_GEOMETRY) + ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->small_prim_cull_info); + + if (ctx->stage == MESA_SHADER_VERTEX) + declare_vb_descriptor_input_sgprs(ctx); } /* VGPRs (first GS, then VS/TES) */ |