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author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2019-09-17 16:46:33 -0700 |
---|---|---|
committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2019-09-20 10:57:05 -0700 |
commit | 10532c68318b9edda58d5a3fa824079799b62555 (patch) | |
tree | 5b5011847b2a69e01bd1d2eb0ad7457add503434 /src | |
parent | dae33052dbfec843d5e997dbd93049d702977fa6 (diff) | |
download | mesa-10532c68318b9edda58d5a3fa824079799b62555.tar.gz |
intel/fs: don't forget the stride at generate_shuffle
During generate_shuffle(), when we use byte sized registers we end up
with a destination stride of 2. We don't take the stride into
consideration when selecting the group offset for the last MOV
operation, which means we end up moving things to the wrong place,
leaving the last few channels untouched. Take the destination stride
in consideration so we don't miss the last channels.
v2: Assert this is not necessary for the IVB special case (Jason).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 1fb50e0da73..6756461bc6d 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -587,12 +587,13 @@ fs_generator::generate_shuffle(fs_inst *inst, struct brw_reg gdst = suboffset(dst, group); struct brw_reg dst_d = retype(spread(gdst, 2), BRW_REGISTER_TYPE_D); + assert(dst.hstride == 1); brw_MOV(p, dst_d, retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D)); brw_MOV(p, byte_offset(dst_d, 4), retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D)); } else { - brw_MOV(p, suboffset(dst, group), + brw_MOV(p, suboffset(dst, group * dst.hstride), retype(brw_VxH_indirect(0, 0), src.type)); } } |