diff options
| author | Danilo Krummrich <dakr@redhat.com> | 2022-08-08 11:55:53 +0200 |
|---|---|---|
| committer | Danilo Krummrich <dakr@redhat.com> | 2022-09-09 17:32:10 +0200 |
| commit | ec60dcd870608b8208778f41745d750bca54b62c (patch) | |
| tree | 4f76269b2bd74b33c94830c20ff3760154271c8b /src/nouveau | |
| parent | 6e2fda15f14d95ead492245698f430b6708329f0 (diff) | |
| download | mesa-ec60dcd870608b8208778f41745d750bca54b62c.tar.gz | |
nv50/ir/nir: avoid 8/16 bit dest regs for OP_MOV
Instructions like
mov u16 %r78s 0x00ff (0)
are dropped, since they're not supported by the HW, hence avoid using
8/16 bit destination registers for OP_MOV and use the full width of the
register instead.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
Diffstat (limited to 'src/nouveau')
| -rw-r--r-- | src/nouveau/codegen/nv50_ir_from_nir.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index 8fa70c5f519..523ae0124e1 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -2509,10 +2509,10 @@ Converter::convert(nir_load_const_instr *insn, uint8_t idx) val = loadImm(getSSA(4), insn->value[idx].u32); break; case 16: - val = loadImm(getSSA(2), insn->value[idx].u16); + val = loadImm(getSSA(4), insn->value[idx].u16); break; case 8: - val = loadImm(getSSA(1), insn->value[idx].u8); + val = loadImm(getSSA(4), insn->value[idx].u8); break; default: unreachable("unhandled bit size!\n"); |