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authorLionel Landwerlin <lionel.g.landwerlin@intel.com>2021-09-22 15:06:58 +0300
committerMarge Bot <emma+marge@anholt.net>2021-11-08 16:48:06 +0000
commit361b3fee3c5ee38821d96660d68ebec2e31e5f47 (patch)
tree242fad1e154aa202bc33c0ab1e4f87d360622475 /src/intel/compiler
parent3b1a5b8f2ba15dfec24b80fcb3f005084c03289e (diff)
downloadmesa-361b3fee3c5ee38821d96660d68ebec2e31e5f47.tar.gz
intel: move away from booleans to identify platforms
v2: Drop changes around GFX_VERx10 == 75 (Luis) v3: Replace (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT) by (devinfo->platform == INTEL_PLATFORM_IVB) Replace (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X) by (devinfo->verx10 >= 45) Replace (devinfo->platform != INTEL_PLATFORM_G4X) by (devinfo->verx10 != 45) v4: Fix crocus typo v5: Rebase v6: Add GFX3, ILK & I965 platforms (Jordan) Move ifdef to code expressions (Jordan) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
Diffstat (limited to 'src/intel/compiler')
-rw-r--r--src/intel/compiler/brw_clip_util.c2
-rw-r--r--src/intel/compiler/brw_disasm.c4
-rw-r--r--src/intel/compiler/brw_eu.h14
-rw-r--r--src/intel/compiler/brw_eu_compact.c21
-rw-r--r--src/intel/compiler/brw_eu_emit.c2
-rw-r--r--src/intel/compiler/brw_eu_validate.c16
-rw-r--r--src/intel/compiler/brw_fs.cpp12
-rw-r--r--src/intel/compiler/brw_fs_generator.cpp15
-rw-r--r--src/intel/compiler/brw_fs_lower_regioning.cpp3
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp4
-rw-r--r--src/intel/compiler/brw_inst.h9
-rw-r--r--src/intel/compiler/brw_ir_fs.h3
-rw-r--r--src/intel/compiler/brw_ir_performance.cpp48
-rw-r--r--src/intel/compiler/brw_nir.c2
-rw-r--r--src/intel/compiler/brw_nir_lower_storage_image.c2
-rw-r--r--src/intel/compiler/brw_schedule_instructions.cpp2
-rw-r--r--src/intel/compiler/brw_vec4_generator.cpp14
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp2
-rw-r--r--src/intel/compiler/brw_vec4_surface_builder.cpp4
-rw-r--r--src/intel/compiler/brw_vec4_visitor.cpp2
-rw-r--r--src/intel/compiler/test_eu_compact.cpp4
-rw-r--r--src/intel/compiler/test_eu_validate.cpp25
22 files changed, 112 insertions, 98 deletions
diff --git a/src/intel/compiler/brw_clip_util.c b/src/intel/compiler/brw_clip_util.c
index 1f334d2bcb9..32c70006933 100644
--- a/src/intel/compiler/brw_clip_util.c
+++ b/src/intel/compiler/brw_clip_util.c
@@ -424,7 +424,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
- if (p->devinfo->ver == 5 || p->devinfo->is_g4x)
+ if (p->devinfo->ver == 5 || p->devinfo->verx10 == 45)
brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
else
brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index acbe9d6f94d..9b1d9017fb6 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -2100,7 +2100,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
brw_sampler_desc_binding_table_index(devinfo, imm_desc),
brw_sampler_desc_sampler(devinfo, imm_desc),
brw_sampler_desc_msg_type(devinfo, imm_desc));
- if (!devinfo->is_g4x) {
+ if (devinfo->verx10 != 45) {
err |= control(file, "sampler target format",
sampler_target_format,
brw_sampler_desc_return_format(devinfo, imm_desc),
@@ -2120,7 +2120,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
devinfo->ver >= 7 ? 0u :
brw_dp_write_desc_write_commit(devinfo, imm_desc));
} else {
- bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x;
+ bool is_965 = devinfo->verx10 == 40;
err |= control(file, "DP read message type",
is_965 ? gfx4_dp_read_port_msg_type :
g45_dp_read_port_msg_type,
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 04256257533..11f2734e175 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -402,7 +402,7 @@ brw_sampler_desc(const struct intel_device_info *devinfo,
else if (devinfo->ver >= 5)
return (desc | SET_BITS(msg_type, 15, 12) |
SET_BITS(simd_mode, 17, 16));
- else if (devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
return desc | SET_BITS(msg_type, 15, 12);
else
return (desc | SET_BITS(return_format, 13, 12) |
@@ -429,7 +429,7 @@ brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc
{
if (devinfo->ver >= 7)
return GET_BITS(desc, 16, 12);
- else if (devinfo->ver >= 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 15, 12);
else
return GET_BITS(desc, 15, 14);
@@ -450,7 +450,7 @@ static inline unsigned
brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo,
uint32_t desc)
{
- assert(devinfo->ver == 4 && !devinfo->is_g4x);
+ assert(devinfo->verx10 == 40);
return GET_BITS(desc, 13, 12);
}
@@ -522,7 +522,7 @@ brw_dp_read_desc(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
- else if (devinfo->ver >= 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
return (SET_BITS(binding_table_index, 7, 0) |
SET_BITS(msg_control, 10, 8) |
SET_BITS(msg_type, 13, 11) |
@@ -540,7 +540,7 @@ brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc_msg_type(devinfo, desc);
- else if (devinfo->ver >= 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 13, 11);
else
return GET_BITS(desc, 13, 12);
@@ -552,7 +552,7 @@ brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc_msg_control(devinfo, desc);
- else if (devinfo->ver >= 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 10, 8);
else
return GET_BITS(desc, 11, 8);
@@ -779,7 +779,7 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo,
} else {
if (devinfo->ver >= 7) {
msg_type = GFX7_DATAPORT_DC_DWORD_SCATTERED_READ;
- } else if (devinfo->ver > 4 || devinfo->is_g4x) {
+ } else if (devinfo->verx10 >= 45) {
msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
} else {
msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c
index 1bda759b185..38c9279ef9f 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1331,7 +1331,7 @@ set_3src_control_index(const struct intel_device_info *devinfo,
(brw_inst_bits(src, 34, 32) << 21) | /* 3b */
(brw_inst_bits(src, 28, 8)); /* 21b */
- if (devinfo->ver >= 9 || devinfo->is_cherryview) {
+ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
uncompacted |=
brw_inst_bits(src, 36, 35) << 24; /* 2b */
}
@@ -1392,7 +1392,7 @@ set_3src_source_index(const struct intel_device_info *devinfo,
(brw_inst_bits(src, 72, 65) << 19) | /* 8b */
(brw_inst_bits(src, 55, 37)); /* 19b */
- if (devinfo->ver >= 9 || devinfo->is_cherryview) {
+ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
uncompacted |=
(brw_inst_bits(src, 126, 125) << 47) | /* 2b */
(brw_inst_bits(src, 105, 104) << 45) | /* 2b */
@@ -1480,7 +1480,7 @@ has_3src_unmapped_bits(const struct intel_device_info *devinfo,
*/
if (devinfo->ver >= 12) {
assert(!brw_inst_bits(src, 7, 7));
- } else if (devinfo->ver >= 9 || devinfo->is_cherryview) {
+ } else if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
assert(!brw_inst_bits(src, 127, 127) &&
!brw_inst_bits(src, 7, 7));
} else {
@@ -1728,7 +1728,7 @@ precompact(const struct intel_device_info *devinfo, brw_inst inst)
* immediate we set.
*/
if (devinfo->ver >= 6 &&
- !(devinfo->is_haswell &&
+ !(devinfo->platform == INTEL_PLATFORM_HSW &&
brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
!(devinfo->ver >= 8 &&
(brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
@@ -2082,7 +2082,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c,
brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7);
brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff);
- if (devinfo->ver >= 9 || devinfo->is_cherryview)
+ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV)
brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3);
}
}
@@ -2125,7 +2125,7 @@ set_uncompacted_3src_source_index(const struct intel_device_info *devinfo,
brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff);
brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff);
- if (devinfo->ver >= 9 || devinfo->is_cherryview) {
+ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3);
brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3);
brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1);
@@ -2339,13 +2339,13 @@ static void
update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
- assert(devinfo->ver == 5 || devinfo->is_g4x);
+ assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X);
/* Jump Count is in units of:
* - uncompacted instructions on G45; and
* - compacted instructions on Gfx5.
*/
- int shift = devinfo->is_g4x ? 1 : 0;
+ int shift = devinfo->platform == INTEL_PLATFORM_G4X ? 1 : 0;
int jump_count_compacted = brw_inst_gfx4_jump_count(devinfo, insn) << shift;
@@ -2462,7 +2462,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
*/
int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1];
- if (devinfo->ver == 4 && !devinfo->is_g4x)
+ if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X)
return;
struct compaction_state c;
@@ -2495,7 +2495,8 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
offset += sizeof(brw_compact_inst);
} else {
/* All uncompacted instructions need to be aligned on G45. */
- if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
+ if ((offset & sizeof(brw_compact_inst)) != 0 &&
+ devinfo->platform == INTEL_PLATFORM_G4X) {
brw_compact_inst *align = store + offset;
memset(align, 0, sizeof(*align));
brw_compact_inst_set_hw_opcode(
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index a8e19cbf0c9..a88be5aba4c 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3544,7 +3544,7 @@ brw_broadcast(struct brw_codegen *p,
/* Use indirect addressing to fetch the specified component. */
if (type_sz(src.type) > 4 &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index 68d41e3e661..8e36e655d09 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -862,7 +862,8 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
ERROR_IF(subreg % 4 != 0,
"Conversions between integer and half-float must be "
"aligned to a DWord on the destination");
- } else if ((devinfo->is_cherryview || devinfo->ver >= 9) &&
+ } else if ((devinfo->platform == INTEL_PLATFORM_CHV ||
+ devinfo->ver >= 9) &&
dst_type == BRW_REGISTER_TYPE_HF) {
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
ERROR_IF(dst_stride != 2 &&
@@ -881,7 +882,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
*/
bool validate_dst_size_and_exec_size_ratio =
!is_mixed_float(devinfo, inst) ||
- !(devinfo->is_cherryview || devinfo->ver >= 9);
+ !(devinfo->platform == INTEL_PLATFORM_CHV || devinfo->ver >= 9);
if (validate_dst_size_and_exec_size_ratio &&
exec_type_size > dst_type_size) {
@@ -900,7 +901,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
* Implementation Restriction: The relaxed alignment rule for byte
* destination (#10.5) is not supported.
*/
- if ((devinfo->ver > 4 || devinfo->is_g4x) && dst_type_is_byte) {
+ if (devinfo->verx10 >= 45 && dst_type_is_byte) {
ERROR_IF(subreg % exec_type_size != 0 &&
subreg % exec_type_size != 1,
"Destination subreg must be aligned to the size of the "
@@ -1820,7 +1821,7 @@ special_requirements_for_handling_double_precision_data_types(
*/
if (is_double_precision &&
brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
+ (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(!is_scalar_region &&
(src_stride % 8 != 0 ||
dst_stride % 8 != 0 ||
@@ -1845,7 +1846,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
+ (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode ||
BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode,
"Indirect addressing is not allowed when the execution type "
@@ -1862,7 +1863,8 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction does not apply to the null register.
*/
if (is_double_precision &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
+ (devinfo->platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC ||
brw_inst_acc_wr_control(devinfo, inst) ||
(BRW_ARCHITECTURE_REGISTER_FILE == file &&
@@ -1949,7 +1951,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
+ (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_no_dd_check(devinfo, inst) ||
brw_inst_no_dd_clear(devinfo, inst),
"DepCtrl is not allowed when the execution type is 64-bit");
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 728ad8865b2..51ab3c4b119 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3829,7 +3829,7 @@ fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_ins
void
fs_visitor::insert_gfx4_send_dependency_workarounds()
{
- if (devinfo->ver != 4 || devinfo->is_g4x)
+ if (devinfo->ver != 4 || devinfo->platform == INTEL_PLATFORM_G4X)
return;
bool progress = false;
@@ -7105,7 +7105,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
for (unsigned i = 0; i < inst->sources; i++) {
/* IVB implements DF scalars as <0;2,1> regions. */
const bool is_scalar_exception = is_uniform(inst->src[i]) &&
- (devinfo->is_haswell || type_sz(inst->src[i].type) != 8);
+ (devinfo->platform == INTEL_PLATFORM_HSW || type_sz(inst->src[i].type) != 8);
const bool is_packed_word_exception =
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
@@ -7384,7 +7384,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
* should
* "Force BFI instructions to be executed always in SIMD8."
*/
- return MIN2(devinfo->is_haswell ? 8 : ~0u,
+ return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u,
get_fpu_lowered_simd_width(devinfo, inst));
case BRW_OPCODE_IF:
@@ -7401,7 +7401,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
/* Unary extended math instructions are limited to SIMD8 on Gfx4 and
* Gfx6. Extended Math Function is limited to SIMD8 with half-float.
*/
- if (devinfo->ver == 6 || (devinfo->ver == 4 && !devinfo->is_g4x))
+ if (devinfo->ver == 6 || devinfo->verx10 == 40)
return MIN2(8, inst->exec_size);
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
return MIN2(8, inst->exec_size);
@@ -8937,7 +8937,7 @@ fs_visitor::allocate_registers(bool allow_spilling)
prog_data->total_scratch = brw_get_scratch_size(last_scratch);
if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) {
- if (devinfo->is_haswell) {
+ if (devinfo->platform == INTEL_PLATFORM_HSW) {
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
* field documentation, Haswell supports a minimum of 2kB of
* scratch space for compute shaders, unlike every other stage
@@ -9328,7 +9328,7 @@ fs_visitor::run_cs(bool allow_spilling)
if (shader_time_index >= 0)
emit_shader_time_begin();
- if (devinfo->is_haswell && prog_data->total_shared > 0) {
+ if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) {
/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
const fs_builder abld = bld.exec_all().group(1, 0);
abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW),
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index a1a74d14a78..8f59e4113d0 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -279,7 +279,7 @@ fs_generator::patch_halt_jumps()
brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH);
}
- if (devinfo->ver == 4 && !devinfo->is_g4x) {
+ if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) {
/* From the g965 PRM:
*
* "[DevBW, DevCL] Erratum: The subfields in mask stack register are
@@ -550,7 +550,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
if (type_sz(reg.type) > 4 &&
((devinfo->verx10 == 70) ||
- devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
@@ -715,7 +715,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
if (type_sz(src.type) > 4 &&
((devinfo->verx10 == 70) ||
- devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
@@ -1418,7 +1418,7 @@ fs_generator::generate_ddy(const fs_inst *inst,
* inherits its FP16 hardware from SKL, so it is not affected.
*/
if (devinfo->ver >= 11 ||
- (devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) {
+ (devinfo->platform == INTEL_PLATFORM_BDW && src.type == BRW_REGISTER_TYPE_HF)) {
src = stride(src, 0, 2, 1);
brw_push_insn_state(p);
@@ -2285,7 +2285,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
src[0], brw_null_reg());
} else {
assert(inst->mlen >= 1);
- assert(devinfo->ver == 5 || devinfo->is_g4x || inst->exec_size == 8);
+ assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8);
gfx4_math(p, dst,
brw_math_function(inst->opcode),
inst->base_mrf, src[0],
@@ -2583,7 +2583,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
struct brw_reg strided = stride(suboffset(src[0], component),
vstride, width, 0);
if (type_sz(src[0].type) > 4 &&
- (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ (devinfo->platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
@@ -2661,7 +2662,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
case BRW_OPCODE_DIM:
- assert(devinfo->is_haswell);
+ assert(devinfo->platform == INTEL_PLATFORM_HSW);
assert(src[0].type == BRW_REGISTER_TYPE_DF);
assert(dst.type == BRW_REGISTER_TYPE_DF);
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp
index c9ce2a814db..c1ff057064a 100644
--- a/src/intel/compiler/brw_fs_lower_regioning.cpp
+++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
@@ -203,7 +203,8 @@ namespace {
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
return (((devinfo->verx10 == 70) ||
- devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ devinfo->platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
(devinfo->verx10 >= 125 &&
brw_reg_type_is_floating_point(inst->src[0].type)) ?
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 5ba9473684e..1d533d233df 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4658,7 +4658,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
(instr->num_components - 1) * type_sz(dest.type);
bool supports_64bit_indirects =
- !devinfo->is_cherryview && !intel_device_info_is_9lp(devinfo);
+ devinfo->platform != INTEL_PLATFORM_CHV && !intel_device_info_is_9lp(devinfo);
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {
@@ -6467,7 +6467,7 @@ setup_imm_df(const fs_builder &bld, double v)
/* gfx7.5 does not support DF immediates straighforward but the DIM
* instruction allows to set the 64-bit immediate value.
*/
- if (devinfo->is_haswell) {
+ if (devinfo->platform == INTEL_PLATFORM_HSW) {
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
ubld.DIM(dst, brw_imm_df(v));
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 2a9e3fbd642..5b531f4f805 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -93,7 +93,7 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
high = hi6; low = lo6; \
} else if (devinfo->ver >= 5) { \
high = hi5; low = lo5; \
- } else if (devinfo->is_g4x) { \
+ } else if (devinfo->verx10 >= 45) { \
high = hi45; low = lo45; \
} else { \
high = hi4; low = lo4; \
@@ -299,7 +299,8 @@ F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8)
FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6)
-FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5)
+FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->verx10 == 45 ||
+ devinfo->ver == 5)
F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6)
F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
@@ -916,7 +917,7 @@ FF(sampler_msg_type,
/* 7: */ MD(16), MD(12),
/* 8: */ MD(16), MD(12),
/* 12: */ MD12(16), MD12(12))
-FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->ver == 4 && !devinfo->is_g4x)
+FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->verx10 == 40)
FD(sampler,
/* 4: */ MD(11), MD(8),
/* 4.5: */ MD(11), MD(8),
@@ -1395,7 +1396,7 @@ F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_i
FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6)
F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6)
-FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5)
+FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->verx10 == 45 || devinfo->ver == 5)
F(subreg_index, /* 4+ */ 22, 18, /* 12+ */ 39, 35)
F(datatype_index, /* 4+ */ 17, 13, /* 12+ */ 34, 30)
F(control_index, /* 4+ */ 12, 8, /* 12+ */ 28, 24)
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index a61e66303b6..6f7bab25272 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -570,7 +570,8 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 ||
(type_sz(exec_type) == 4 && is_dword_multiply))
- return devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
+ return devinfo->platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125;
else if (brw_reg_type_is_floating_point(dst_type))
diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index 2a7dc787afe..e3af579c8dd 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -367,7 +367,7 @@ namespace {
else
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 8, 4, 12, 0, 0);
- } else if (devinfo->is_haswell) {
+ } else if (devinfo->verx10 >= 75) {
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 16, 0, 0);
} else {
@@ -392,7 +392,7 @@ namespace {
else
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 8, 4, 12, 0, 0);
- } else if (devinfo->is_haswell) {
+ } else if (devinfo->verx10 >= 75) {
if (info.tx == BRW_REGISTER_TYPE_F)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 12, 8 /* XXX */, 18, 0, 0);
@@ -422,7 +422,7 @@ namespace {
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->ver >= 7)
@@ -442,7 +442,7 @@ namespace {
else
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- } else if (devinfo->is_haswell) {
+ } else if (devinfo->verx10 >= 75) {
if (info.tx == BRW_REGISTER_TYPE_F)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 12, 8 /* XXX */, 18, 0, 0);
@@ -472,7 +472,7 @@ namespace {
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->ver >= 7)
@@ -488,7 +488,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else
@@ -524,7 +524,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_em, -2, 4, 0, 0, 4,
0, 16, 0, 0, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_em, 0, 2, 0, 0, 2,
0, 12, 0, 0, 0, 0);
else
@@ -535,7 +535,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_em, -2, 4, 0, 0, 8,
0, 24, 0, 0, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_em, 0, 2, 0, 0, 4,
0, 20, 0, 0, 0, 0);
else
@@ -603,7 +603,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_null, 8, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_null, 6, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
else
@@ -614,7 +614,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else
@@ -625,7 +625,7 @@ namespace {
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 1, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->ver >= 6)
@@ -643,7 +643,7 @@ namespace {
return calculate_desc(info, unit_fpu, 16, 6, 0, 0, 6,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 20, 6, 0, 0, 6,
0, 10 /* XXX */, 6 /* XXX */,
16 /* XXX */, 0, 0);
@@ -663,7 +663,7 @@ namespace {
return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0,
0, 10 /* XXX */, 6 /* XXX */,
16 /* XXX */, 0, 0);
@@ -679,7 +679,7 @@ namespace {
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->ver >= 7)
@@ -695,7 +695,7 @@ namespace {
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 2, 0, 0, 2, 0,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 36, 0, 0, 6, 0,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->ver >= 7)
@@ -714,7 +714,7 @@ namespace {
return calculate_desc(info, unit_fpu, 20 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 24 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
@@ -736,7 +736,7 @@ namespace {
42 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 44 /* XXX */, 0,
0, 44 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
@@ -760,7 +760,7 @@ namespace {
0, 4 /* XXX */,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 10 /* XXX */, 4 /* XXX */, 0,
0, 4 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
@@ -782,7 +782,7 @@ namespace {
0, 8 /* XXX */,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0 /* XXX */, 8 /* XXX */, 0,
0, 8 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
@@ -800,7 +800,7 @@ namespace {
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
@@ -825,7 +825,7 @@ namespace {
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 4 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
@@ -846,7 +846,7 @@ namespace {
6 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 26 /* XXX */, 0, 0,
6 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
@@ -864,7 +864,7 @@ namespace {
8 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 38 /* XXX */, 0, 0,
8 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
@@ -883,7 +883,7 @@ namespace {
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
- else if (devinfo->is_haswell)
+ else if (devinfo->verx10 >= 75)
return calculate_desc(info, unit_fpu, 14 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 1d69eebc852..d50feb093bb 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -775,7 +775,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
/* See also brw_nir_trig_workarounds.py */
if (compiler->precise_trig &&
- !(devinfo->ver >= 10 || devinfo->is_kabylake))
+ !(devinfo->ver >= 10 || devinfo->platform == INTEL_PLATFORM_KBL))
OPT(brw_nir_apply_trig_workarounds);
if (devinfo->ver >= 12)
diff --git a/src/intel/compiler/brw_nir_lower_storage_image.c b/src/intel/compiler/brw_nir_lower_storage_image.c
index a9946694f3b..57f553c4ac6 100644
--- a/src/intel/compiler/brw_nir_lower_storage_image.c
+++ b/src/intel/compiler/brw_nir_lower_storage_image.c
@@ -200,7 +200,7 @@ image_address(nir_builder *b, const struct intel_device_info *devinfo,
/* Multiply by the Bpp value. */
addr = nir_imul(b, idx, nir_channel(b, stride, 0));
- if (devinfo->ver < 8 && !devinfo->is_baytrail) {
+ if (devinfo->ver < 8 && devinfo->platform != INTEL_PLATFORM_BYT) {
/* Take into account the two dynamically specified shifts. Both are
* used to implement swizzling of X-tiled surfaces. For Y-tiled
* surfaces only one bit needs to be XOR-ed with bit 6 of the memory
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index ae24bff2271..5efea03e04a 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -975,7 +975,7 @@ schedule_node::schedule_node(backend_instruction *inst,
if (!sched->post_reg_alloc)
this->latency = 1;
else if (devinfo->ver >= 6)
- set_latency_gfx7(devinfo->is_haswell);
+ set_latency_gfx7(devinfo->verx10 == 75);
else
set_latency_gfx4();
}
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 5f880951e68..7ade12344ec 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -130,7 +130,7 @@ generate_tex(struct brw_codegen *p,
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gfx7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
- assert(devinfo->is_haswell);
+ assert(devinfo->verx10 == 75);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -738,7 +738,8 @@ static void
generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
{
const struct intel_device_info *devinfo = p->devinfo;
- const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
+ const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB ||
+ devinfo->platform == INTEL_PLATFORM_BYT;
/* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
*
@@ -1058,7 +1059,8 @@ generate_tcs_create_barrier_header(struct brw_codegen *p,
struct brw_reg dst)
{
const struct intel_device_info *devinfo = p->devinfo;
- const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
+ const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB ||
+ devinfo->platform == INTEL_PLATFORM_BYT;
struct brw_reg m0_2 = get_element_ud(dst, 2);
unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
@@ -1158,7 +1160,7 @@ generate_scratch_read(struct brw_codegen *p,
if (devinfo->ver >= 6)
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
- else if (devinfo->ver == 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@@ -1301,7 +1303,7 @@ generate_pull_constant_load(struct brw_codegen *p,
if (devinfo->ver >= 6)
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
- else if (devinfo->ver == 5 || devinfo->is_g4x)
+ else if (devinfo->verx10 >= 45)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@@ -2188,7 +2190,7 @@ generate_code(struct brw_codegen *p,
break;
case BRW_OPCODE_DIM:
- assert(devinfo->is_haswell);
+ assert(devinfo->verx10 == 75);
assert(src[0].type == BRW_REGISTER_TYPE_DF);
assert(dst.type == BRW_REGISTER_TYPE_DF);
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 435f79dad59..4600368194d 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -288,7 +288,7 @@ setup_imm_df(const vec4_builder &bld, double v)
/* gfx7.5 does not support DF immediates straighforward but the DIM
* instruction allows to set the 64-bit immediate value.
*/
- if (devinfo->is_haswell) {
+ if (devinfo->verx10 == 75) {
const vec4_builder ubld = bld.exec_all();
const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_DF);
ubld.DIM(dst, brw_imm_df(v));
diff --git a/src/intel/compiler/brw_vec4_surface_builder.cpp b/src/intel/compiler/brw_vec4_surface_builder.cpp
index 5418f600545..fce3133bef8 100644
--- a/src/intel/compiler/brw_vec4_surface_builder.cpp
+++ b/src/intel/compiler/brw_vec4_surface_builder.cpp
@@ -163,7 +163,7 @@ namespace brw {
unsigned dims, unsigned size,
brw_predicate pred)
{
- const bool has_simd4x2 = bld.shader->devinfo->is_haswell;
+ const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75;
emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(),
emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims,
@@ -184,7 +184,7 @@ namespace brw {
unsigned dims, unsigned rsize, unsigned op,
brw_predicate pred)
{
- const bool has_simd4x2 = bld.shader->devinfo->is_haswell;
+ const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75;
/* Zip the components of both sources, they are represented as the X
* and Y components of the same vector.
diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp
index a10f545d5b1..3ad8868ac5f 100644
--- a/src/intel/compiler/brw_vec4_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_visitor.cpp
@@ -819,7 +819,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
bool
vec4_visitor::is_high_sampler(src_reg sampler)
{
- if (!devinfo->is_haswell)
+ if (devinfo->verx10 != 75)
return false;
return sampler.file != IMM || sampler.ud >= 16;
diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp
index a7d5e919ce8..16e2e4c6100 100644
--- a/src/intel/compiler/test_eu_compact.cpp
+++ b/src/intel/compiler/test_eu_compact.cpp
@@ -99,7 +99,7 @@ clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst)
brw_inst_set_bits(inst, 127, 111, 0);
}
- if (devinfo->ver == 8 && !devinfo->is_cherryview &&
+ if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV &&
is_3src(devinfo, brw_inst_opcode(devinfo, inst))) {
brw_inst_set_bits(inst, 105, 105, 0);
brw_inst_set_bits(inst, 84, 84, 0);
@@ -119,7 +119,7 @@ skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit)
return true;
if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
- if (devinfo->ver >= 9 || devinfo->is_cherryview) {
+ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
if (bit == 127)
return true;
} else {
diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp
index 6c267d96b5f..ac1cad0d563 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -1234,7 +1234,7 @@ TEST_P(validation_test, byte_destination_relaxed_alignment)
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1);
- if (devinfo.ver > 4 || devinfo.is_g4x) {
+ if (devinfo.verx10 >= 45) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@@ -1416,7 +1416,7 @@ TEST_P(validation_test, half_float_conversion)
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
}
- if (devinfo.is_cherryview || devinfo.ver >= 9)
+ if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_gfx9, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@@ -1603,7 +1603,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0)
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr);
- if (devinfo.is_cherryview || devinfo.ver >= 9)
+ if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@@ -1686,7 +1686,7 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc)
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
- if (devinfo.is_cherryview || devinfo.ver >= 9)
+ if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@@ -1830,7 +1830,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst)
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
- if (devinfo.is_cherryview || devinfo.ver >= 9)
+ if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@@ -2312,7 +2312,8 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
- if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
+ if (devinfo.platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@@ -2444,7 +2445,8 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
- if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
+ if (devinfo.platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@@ -2591,7 +2593,8 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
- if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
+ if (devinfo.platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@@ -2607,7 +2610,8 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF),
retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF),
retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF));
- if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
+ if (devinfo.platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(&devinfo)) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@@ -2809,7 +2813,8 @@ TEST_P(validation_test, qword_low_power_no_depctrl)
brw_inst_set_no_dd_check(&devinfo, last_inst, inst[i].no_dd_check);
brw_inst_set_no_dd_clear(&devinfo, last_inst, inst[i].no_dd_clear);
- if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
+ if (devinfo.platform == INTEL_PLATFORM_CHV ||
+ intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
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