diff options
| author | Rob Clark <robdclark@chromium.org> | 2022-12-29 08:55:25 -0800 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2023-02-01 17:28:41 +0000 |
| commit | 13fe9c3e6350c640ad53443369605b3ed5b8112b (patch) | |
| tree | 412c177a7842fdb40ace31b255cfdac945330ee0 /src/freedreno/ir3 | |
| parent | 951d963565fe043754bec3e0a401eb0430d439a7 (diff) | |
| download | mesa-13fe9c3e6350c640ad53443369605b3ed5b8112b.tar.gz | |
freedreno/ir3: Scalarize load_ssbo
The benefits of turning it into isam (which needs to be scalar as the
SSBO is sampled as a single component R32 texture) outweigh the benefits
of vectorizing.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20975>
Diffstat (limited to 'src/freedreno/ir3')
| -rw-r--r-- | src/freedreno/ir3/ir3_nir.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 1830fd2ce13..dd9cc0885ad 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -39,6 +39,14 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, { unsigned byte_size = bit_size / 8; + /* Don't vectorize load_ssbo's that we could otherwise lower to isam, + * as the tex cache benefit outweighs the benefit of vectorizing + */ + if ((low->intrinsic == nir_intrinsic_load_ssbo) && + (nir_intrinsic_access(low) & ACCESS_CAN_REORDER)) { + return false; + } + if (low->intrinsic != nir_intrinsic_load_ubo) { return bit_size <= 32 && align_mul >= byte_size && align_offset % byte_size == 0 && @@ -628,6 +636,8 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s) bool progress = false; + NIR_PASS_V(s, nir_lower_io_to_scalar, nir_var_mem_ssbo); + if (so->key.has_gs || so->key.tessellation) { switch (so->type) { case MESA_SHADER_VERTEX: |