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| author | Ian Romanick <ian.d.romanick@intel.com> | 2018-06-27 11:41:19 -0700 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2018-12-17 13:47:06 -0800 |
| commit | 09b7e1d8e4e07e7c51debb20e85e213ab209985f (patch) | |
| tree | 6055f454c575bbedf5811c617dbbe1f0f7b71e14 /src/freedreno/ir3/ir3_nir.c | |
| parent | 4cd1a0be76883c2b13aae8c97972e8f1404d06f7 (diff) | |
| download | mesa-09b7e1d8e4e07e7c51debb20e85e213ab209985f.tar.gz | |
nir/opt_peephole_select: Don't try to remove flow control around indirect loads
That flow control may be trying to avoid invalid loads. On at least
some platforms, those loads can also be expensive.
No shader-db changes on any Intel platform (even with the later patch
"intel/compiler: More peephole select").
v2: Add a 'indirect_load_ok' flag to nir_opt_peephole_select. Suggested
by Rob. See also the big comment in src/intel/compiler/brw_nir.c.
v3: Use nir_deref_instr_has_indirect instead of deref_has_indirect (from
nir_lower_io_arrays_to_elements.c).
v4: Fix inverted condition in brw_nir.c. Noticed by Lionel.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Diffstat (limited to 'src/freedreno/ir3/ir3_nir.c')
| -rw-r--r-- | src/freedreno/ir3/ir3_nir.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 70c01ee0593..112c0928529 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -97,7 +97,7 @@ ir3_optimize_loop(nir_shader *s) progress |= OPT(s, nir_opt_gcm, true); else if (gcm == 2) progress |= OPT(s, nir_opt_gcm, false); - progress |= OPT(s, nir_opt_peephole_select, 16); + progress |= OPT(s, nir_opt_peephole_select, 16, true); progress |= OPT(s, nir_opt_intrinsics); progress |= OPT(s, nir_opt_algebraic); progress |= OPT(s, nir_opt_constant_folding); |