aco: return references in instruction cast methods

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8595>

1 files changed, 106 insertions, 106 deletions

diff --git a/src/amd/compiler/aco_opt_value_numbering.cpp b/src/amd/compiler/aco_opt_value_numbering.cpp
index de0eb94befa..42aa701d40e 100644
--- a/src/amd/compiler/aco_opt_value_numbering.cpp
+++ b/src/amd/compiler/aco_opt_value_numbering.cpp
@@ -178,121 +178,121 @@ struct InstrPred {
          return false;
 
       if (a->isVOP3()) {
-         VOP3_instruction* a3 = a->vop3();
-         VOP3_instruction* b3 = b->vop3();
+         VOP3_instruction& a3 = a->vop3();
+         VOP3_instruction& b3 = b->vop3();
          for (unsigned i = 0; i < 3; i++) {
-            if (a3->abs[i] != b3->abs[i] ||
-                a3->neg[i] != b3->neg[i])
+            if (a3.abs[i] != b3.abs[i] ||
+                a3.neg[i] != b3.neg[i])
                return false;
          }
-         return a3->clamp == b3->clamp &&
-                a3->omod == b3->omod &&
-                a3->opsel == b3->opsel;
+         return a3.clamp == b3.clamp &&
+                a3.omod == b3.omod &&
+                a3.opsel == b3.opsel;
       }
       if (a->isDPP()) {
-         DPP_instruction* aDPP = a->dpp();
-         DPP_instruction* bDPP = b->dpp();
-         return aDPP->pass_flags == bDPP->pass_flags &&
-                aDPP->dpp_ctrl == bDPP->dpp_ctrl &&
-                aDPP->bank_mask == bDPP->bank_mask &&
-                aDPP->row_mask == bDPP->row_mask &&
-                aDPP->bound_ctrl == bDPP->bound_ctrl &&
-                aDPP->abs[0] == bDPP->abs[0] &&
-                aDPP->abs[1] == bDPP->abs[1] &&
-                aDPP->neg[0] == bDPP->neg[0] &&
-                aDPP->neg[1] == bDPP->neg[1];
+         DPP_instruction& aDPP = a->dpp();
+         DPP_instruction& bDPP = b->dpp();
+         return aDPP.pass_flags == bDPP.pass_flags &&
+                aDPP.dpp_ctrl == bDPP.dpp_ctrl &&
+                aDPP.bank_mask == bDPP.bank_mask &&
+                aDPP.row_mask == bDPP.row_mask &&
+                aDPP.bound_ctrl == bDPP.bound_ctrl &&
+                aDPP.abs[0] == bDPP.abs[0] &&
+                aDPP.abs[1] == bDPP.abs[1] &&
+                aDPP.neg[0] == bDPP.neg[0] &&
+                aDPP.neg[1] == bDPP.neg[1];
       }
       if (a->isSDWA()) {
-         SDWA_instruction* aSDWA = a->sdwa();
-         SDWA_instruction* bSDWA = b->sdwa();
-         return aSDWA->sel[0] == bSDWA->sel[0] &&
-                aSDWA->sel[1] == bSDWA->sel[1] &&
-                aSDWA->dst_sel == bSDWA->dst_sel &&
-                aSDWA->abs[0] == bSDWA->abs[0] &&
-                aSDWA->abs[1] == bSDWA->abs[1] &&
-                aSDWA->neg[0] == bSDWA->neg[0] &&
-                aSDWA->neg[1] == bSDWA->neg[1] &&
-                aSDWA->dst_preserve == bSDWA->dst_preserve &&
-                aSDWA->clamp == bSDWA->clamp &&
-                aSDWA->omod == bSDWA->omod;
+         SDWA_instruction& aSDWA = a->sdwa();
+         SDWA_instruction& bSDWA = b->sdwa();
+         return aSDWA.sel[0] == bSDWA.sel[0] &&
+                aSDWA.sel[1] == bSDWA.sel[1] &&
+                aSDWA.dst_sel == bSDWA.dst_sel &&
+                aSDWA.abs[0] == bSDWA.abs[0] &&
+                aSDWA.abs[1] == bSDWA.abs[1] &&
+                aSDWA.neg[0] == bSDWA.neg[0] &&
+                aSDWA.neg[1] == bSDWA.neg[1] &&
+                aSDWA.dst_preserve == bSDWA.dst_preserve &&
+                aSDWA.clamp == bSDWA.clamp &&
+                aSDWA.omod == bSDWA.omod;
       }
 
       switch (a->format) {
          case Format::SOPK: {
             if (a->opcode == aco_opcode::s_getreg_b32)
                return false;
-            SOPK_instruction* aK = a->sopk();
-            SOPK_instruction* bK = b->sopk();
-            return aK->imm == bK->imm;
+            SOPK_instruction& aK = a->sopk();
+            SOPK_instruction& bK = b->sopk();
+            return aK.imm == bK.imm;
          }
          case Format::SMEM: {
-            SMEM_instruction* aS = a->smem();
-            SMEM_instruction* bS = b->smem();
+            SMEM_instruction& aS = a->smem();
+            SMEM_instruction& bS = b->smem();
             /* isel shouldn't be creating situations where this assertion fails */
-            assert(aS->prevent_overflow == bS->prevent_overflow);
-            return aS->sync.can_reorder() && bS->sync.can_reorder() &&
-                   aS->sync == bS->sync && aS->glc == bS->glc && aS->dlc == bS->dlc &&
-                   aS->nv == bS->nv && aS->disable_wqm == bS->disable_wqm &&
-                   aS->prevent_overflow == bS->prevent_overflow;
+            assert(aS.prevent_overflow == bS.prevent_overflow);
+            return aS.sync.can_reorder() && bS.sync.can_reorder() &&
+                   aS.sync == bS.sync && aS.glc == bS.glc && aS.dlc == bS.dlc &&
+                   aS.nv == bS.nv && aS.disable_wqm == bS.disable_wqm &&
+                   aS.prevent_overflow == bS.prevent_overflow;
          }
          case Format::VINTRP: {
-            Interp_instruction* aI = a->vintrp();
-            Interp_instruction* bI = b->vintrp();
-            if (aI->attribute != bI->attribute)
+            Interp_instruction& aI = a->vintrp();
+            Interp_instruction& bI = b->vintrp();
+            if (aI.attribute != bI.attribute)
                return false;
-            if (aI->component != bI->component)
+            if (aI.component != bI.component)
                return false;
             return true;
          }
          case Format::VOP3P: {
-            VOP3P_instruction* a3P = a->vop3p();
-            VOP3P_instruction* b3P = b->vop3p();
+            VOP3P_instruction& a3P = a->vop3p();
+            VOP3P_instruction& b3P = b->vop3p();
             for (unsigned i = 0; i < 3; i++) {
-               if (a3P->neg_lo[i] != b3P->neg_lo[i] ||
-                   a3P->neg_hi[i] != b3P->neg_hi[i])
+               if (a3P.neg_lo[i] != b3P.neg_lo[i] ||
+                   a3P.neg_hi[i] != b3P.neg_hi[i])
                   return false;
             }
-            return a3P->opsel_lo == b3P->opsel_lo &&
-                   a3P->opsel_hi == b3P->opsel_hi &&
-                   a3P->clamp == b3P->clamp;
+            return a3P.opsel_lo == b3P.opsel_lo &&
+                   a3P.opsel_hi == b3P.opsel_hi &&
+                   a3P.clamp == b3P.clamp;
          }
          case Format::PSEUDO_REDUCTION: {
-            Pseudo_reduction_instruction *aR = a->reduction();
-            Pseudo_reduction_instruction *bR = b->reduction();
-            return aR->pass_flags == bR->pass_flags &&
-                   aR->reduce_op == bR->reduce_op &&
-                   aR->cluster_size == bR->cluster_size;
+            Pseudo_reduction_instruction& aR = a->reduction();
+            Pseudo_reduction_instruction& bR = b->reduction();
+            return aR.pass_flags == bR.pass_flags &&
+                   aR.reduce_op == bR.reduce_op &&
+                   aR.cluster_size == bR.cluster_size;
          }
          case Format::MTBUF: {
-            MTBUF_instruction* aM = a->mtbuf();
-            MTBUF_instruction* bM = b->mtbuf();
-            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
-                   aM->sync == bM->sync &&
-                   aM->dfmt == bM->dfmt &&
-                   aM->nfmt == bM->nfmt &&
-                   aM->offset == bM->offset &&
-                   aM->offen == bM->offen &&
-                   aM->idxen == bM->idxen &&
-                   aM->glc == bM->glc &&
-                   aM->dlc == bM->dlc &&
-                   aM->slc == bM->slc &&
-                   aM->tfe == bM->tfe &&
-                   aM->disable_wqm == bM->disable_wqm;
+            MTBUF_instruction& aM = a->mtbuf();
+            MTBUF_instruction& bM = b->mtbuf();
+            return aM.sync.can_reorder() && bM.sync.can_reorder() &&
+                   aM.sync == bM.sync &&
+                   aM.dfmt == bM.dfmt &&
+                   aM.nfmt == bM.nfmt &&
+                   aM.offset == bM.offset &&
+                   aM.offen == bM.offen &&
+                   aM.idxen == bM.idxen &&
+                   aM.glc == bM.glc &&
+                   aM.dlc == bM.dlc &&
+                   aM.slc == bM.slc &&
+                   aM.tfe == bM.tfe &&
+                   aM.disable_wqm == bM.disable_wqm;
          }
          case Format::MUBUF: {
-            MUBUF_instruction* aM = a->mubuf();
-            MUBUF_instruction* bM = b->mubuf();
-            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
-                   aM->sync == bM->sync &&
-                   aM->offset == bM->offset &&
-                   aM->offen == bM->offen &&
-                   aM->idxen == bM->idxen &&
-                   aM->glc == bM->glc &&
-                   aM->dlc == bM->dlc &&
-                   aM->slc == bM->slc &&
-                   aM->tfe == bM->tfe &&
-                   aM->lds == bM->lds &&
-                   aM->disable_wqm == bM->disable_wqm;
+            MUBUF_instruction& aM = a->mubuf();
+            MUBUF_instruction& bM = b->mubuf();
+            return aM.sync.can_reorder() && bM.sync.can_reorder() &&
+                   aM.sync == bM.sync &&
+                   aM.offset == bM.offset &&
+                   aM.offen == bM.offen &&
+                   aM.idxen == bM.idxen &&
+                   aM.glc == bM.glc &&
+                   aM.dlc == bM.dlc &&
+                   aM.slc == bM.slc &&
+                   aM.tfe == bM.tfe &&
+                   aM.lds == bM.lds &&
+                   aM.disable_wqm == bM.disable_wqm;
          }
          /* we want to optimize these in NIR and don't hassle with load-store dependencies */
          case Format::FLAT:
@@ -308,31 +308,31 @@ struct InstrPred {
                 a->opcode != aco_opcode::ds_permute_b32 &&
                 a->opcode != aco_opcode::ds_swizzle_b32)
                return false;
-            DS_instruction* aD = a->ds();
-            DS_instruction* bD = b->ds();
-            return aD->sync.can_reorder() && bD->sync.can_reorder() &&
-                   aD->sync == bD->sync &&
-                   aD->pass_flags == bD->pass_flags &&
-                   aD->gds == bD->gds &&
-                   aD->offset0 == bD->offset0 &&
-                   aD->offset1 == bD->offset1;
+            DS_instruction& aD = a->ds();
+            DS_instruction& bD = b->ds();
+            return aD.sync.can_reorder() && bD.sync.can_reorder() &&
+                   aD.sync == bD.sync &&
+                   aD.pass_flags == bD.pass_flags &&
+                   aD.gds == bD.gds &&
+                   aD.offset0 == bD.offset0 &&
+                   aD.offset1 == bD.offset1;
          }
          case Format::MIMG: {
-            MIMG_instruction* aM = a->mimg();
-            MIMG_instruction* bM = b->mimg();
-            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
-                   aM->sync == bM->sync &&
-                   aM->dmask == bM->dmask &&
-                   aM->unrm == bM->unrm &&
-                   aM->glc == bM->glc &&
-                   aM->slc == bM->slc &&
-                   aM->tfe == bM->tfe &&
-                   aM->da == bM->da &&
-                   aM->lwe == bM->lwe &&
-                   aM->r128 == bM->r128 &&
-                   aM->a16 == bM->a16 &&
-                   aM->d16 == bM->d16 &&
-                   aM->disable_wqm == bM->disable_wqm;
+            MIMG_instruction& aM = a->mimg();
+            MIMG_instruction& bM = b->mimg();
+            return aM.sync.can_reorder() && bM.sync.can_reorder() &&
+                   aM.sync == bM.sync &&
+                   aM.dmask == bM.dmask &&
+                   aM.unrm == bM.unrm &&
+                   aM.glc == bM.glc &&
+                   aM.slc == bM.slc &&
+                   aM.tfe == bM.tfe &&
+                   aM.da == bM.da &&
+                   aM.lwe == bM.lwe &&
+                   aM.r128 == bM.r128 &&
+                   aM.a16 == bM.a16 &&
+                   aM.d16 == bM.d16 &&
+                   aM.disable_wqm == bM.disable_wqm;
          }
          default:
             return true;