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| author | Timur Kristóf <timur.kristof@gmail.com> | 2019-10-24 18:55:07 +0200 |
|---|---|---|
| committer | Timur Kristóf <timur.kristof@gmail.com> | 2019-10-25 10:10:42 +0200 |
| commit | c037ba1bb7aba99bd15e063bbdbc6d4c68cf2384 (patch) | |
| tree | fb4333e1c5c0d29ee7d761710d38a0f9eb87d0c2 /src/amd/compiler/README | |
| parent | 09d676d81ab6e604f73f65ad696a9996312f93a4 (diff) | |
| download | mesa-c037ba1bb7aba99bd15e063bbdbc6d4c68cf2384.tar.gz | |
aco/gfx10: Mitigate LdsBranchVmemWARHazard.
There is a hazard caused by there is a branch between a
VMEM/GLOBAL/SCRATCH instruction and a DS instruction.
This commit adds a workaround that avoids the problem.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Diffstat (limited to 'src/amd/compiler/README')
| -rw-r--r-- | src/amd/compiler/README | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/amd/compiler/README b/src/amd/compiler/README index 620b4bcf63c..822ecd79cbc 100644 --- a/src/amd/compiler/README +++ b/src/amd/compiler/README @@ -200,3 +200,12 @@ Mitigated by: A VALU instruction that writes an SGPR (or has a valid SDST operand), or `s_waitcnt_depctr 0xfffe`. Note: `s_waitcnt_depctr` is an internal instruction, so there is no further information about what it does or what its operand means. + +### LdsBranchVmemWARHazard + +Triggered by: +VMEM/GLOBAL/SCRATCH instruction, then a branch, then a DS instruction, +or vice versa: DS instruction, then a branch, then a VMEM/GLOBAL/SCRATCH instruction. + +Mitigated by: +Only `s_waitcnt_vscnt null, 0`. Needed even if the first instruction is a load. |