radv: stop using the pipeline for determining the null export workaround

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>

3 files changed, 47 insertions, 28 deletions

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 00303b0ac6e..03583d1b287 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1842,14 +1842,16 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 static void
 radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_part *ps_epilog)
 {
-   struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
    struct radv_shader *ps_shader = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
+   const struct radv_device *device = cmd_buffer->device;
 
    if (cmd_buffer->state.emitted_ps_epilog == ps_epilog)
       return;
 
    uint32_t col_format = ps_epilog->spi_shader_col_format;
-   if (pipeline->need_null_export_workaround && !col_format)
+   bool need_null_export_workaround =
+      radv_needs_null_export_workaround(device, ps_shader, cmd_buffer->state.custom_blend_mode);
+   if (need_null_export_workaround && !col_format)
       col_format = V_028714_SPI_SHADER_32_R;
    radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, col_format);
    radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK,
@@ -9051,8 +9053,12 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
          }
 
          cmd_buffer->state.col_format_non_compacted = ps_epilog->spi_shader_col_format;
-         if (cmd_buffer->state.graphics_pipeline->need_null_export_workaround &&
-             !cmd_buffer->state.col_format_non_compacted)
+
+         bool need_null_export_workaround = radv_needs_null_export_workaround(
+            device, cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT],
+            cmd_buffer->state.custom_blend_mode);
+
+         if (need_null_export_workaround && !cmd_buffer->state.col_format_non_compacted)
             cmd_buffer->state.col_format_non_compacted = V_028714_SPI_SHADER_32_R;
          if (device->physical_device->rad_info.rbplus_allowed)
             cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 4407fce587c..7a4f256abb4 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -3957,6 +3957,37 @@ radv_is_fast_linking_enabled(const VkGraphicsPipelineCreateInfo *pCreateInfo)
    return !(pCreateInfo->flags & VK_PIPELINE_CREATE_LINK_TIME_OPTIMIZATION_BIT_EXT);
 }
 
+bool
+radv_needs_null_export_workaround(const struct radv_device *device, const struct radv_shader *ps,
+                                  unsigned custom_blend_mode)
+{
+   const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
+
+   if (!ps)
+      return false;
+
+   /* Ensure that some export memory is always allocated, for two reasons:
+    *
+    * 1) Correctness: The hardware ignores the EXEC mask if no export
+    *    memory is allocated, so KILL and alpha test do not work correctly
+    *    without this.
+    * 2) Performance: Every shader needs at least a NULL export, even when
+    *    it writes no color/depth output. The NULL export instruction
+    *    stalls without this setting.
+    *
+    * Don't add this to CB_SHADER_MASK.
+    *
+    * GFX10 supports pixel shaders without exports by setting both the
+    * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
+    * instructions if any are present.
+    *
+    * GFX11 requires one color output, otherwise the DCC decompression does nothing.
+    */
+   return (gfx_level <= GFX9 || ps->info.ps.can_discard ||
+           (custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX11 && gfx_level >= GFX11)) &&
+          !ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask;
+}
+
 static VkResult
 radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv_device *device,
                             struct vk_pipeline_cache *cache,
@@ -4051,29 +4082,9 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
       blend.cb_shader_mask &= ps->info.ps.colors_written;
    }
 
-   /* Ensure that some export memory is always allocated, for two reasons:
-    *
-    * 1) Correctness: The hardware ignores the EXEC mask if no export
-    *    memory is allocated, so KILL and alpha test do not work correctly
-    *    without this.
-    * 2) Performance: Every shader needs at least a NULL export, even when
-    *    it writes no color/depth output. The NULL export instruction
-    *    stalls without this setting.
-    *
-    * Don't add this to CB_SHADER_MASK.
-    *
-    * GFX10 supports pixel shaders without exports by setting both the
-    * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
-    * instructions if any are present.
-    *
-    * GFX11 requires one color output, otherwise the DCC decompression does nothing.
-    */
-   pipeline->need_null_export_workaround =
-      (device->physical_device->rad_info.gfx_level <= GFX9 || (ps && ps->info.ps.can_discard) ||
-       (extra && extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX11 &&
-        device->physical_device->rad_info.gfx_level >= GFX11)) &&
-      ps && !ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask;
-   if (pipeline->need_null_export_workaround && !blend.spi_shader_col_format) {
+   unsigned custom_blend_mode = extra ? extra->custom_blend_mode : 0;
+   if (radv_needs_null_export_workaround(device, ps, custom_blend_mode) &&
+       !blend.spi_shader_col_format) {
       blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
       pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R;
    }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e496f658770..7c081ca1cca 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1958,6 +1958,9 @@ struct radv_ps_epilog_key radv_generate_ps_epilog_key(const struct radv_device *
                                                       const struct radv_ps_epilog_state *state,
                                                       bool disable_mrt_compaction);
 
+bool radv_needs_null_export_workaround(const struct radv_device *device,
+                                       const struct radv_shader *ps, unsigned custom_blend_mode);
+
 void radv_cmd_buffer_reset_rendering(struct radv_cmd_buffer *cmd_buffer);
 bool radv_cmd_buffer_upload_alloc_aligned(struct radv_cmd_buffer *cmd_buffer, unsigned size,
                                           unsigned alignment,
@@ -2232,7 +2235,6 @@ struct radv_graphics_pipeline {
    bool uses_drawid;
    bool uses_baseinstance;
 
-   bool need_null_export_workaround;
    /* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
    bool force_vrs_per_vertex;