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authorEric Anholt <eric@anholt.net>2012-10-03 10:03:22 -0700
committerIan Romanick <ian.d.romanick@intel.com>2013-02-19 16:06:56 -0800
commit4e35ffa762d763820b7defc14af564b2a02c61c8 (patch)
tree634dcb6f6900c8e4f9e4c93b93d3a8c66a2c2087
parent15693b7925ccdd45bbb60b375ce6b7a3f60bfa3e (diff)
downloadmesa-4e35ffa762d763820b7defc14af564b2a02c61c8.tar.gz
i965/vs: Try again when we've successfully spilled a reg.
Before, we'd spill one reg, then continue on without actually register allocating, then assertion fail when we tried to use a vgrf number as a register number. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit d4bcc6591812ebe72a363cf98371de5e5016f481) This should have been picked when 9237f0e was picked. Bugzill: https://bugs.freedesktop.org/show_bug.cgi?id=59700
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_emit.cpp5
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp17
3 files changed, 16 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 407e227a51d..dce3c89575d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -312,8 +312,8 @@ public:
int setup_attributes(int payload_reg);
int setup_uniforms(int payload_reg);
void setup_payload();
- void reg_allocate_trivial();
- void reg_allocate();
+ bool reg_allocate_trivial();
+ bool reg_allocate();
void evaluate_spill_costs(float *spill_costs, bool *no_spill);
int choose_spill_reg(struct ra_graph *g);
void spill_reg(int spill_reg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 55bff7bb449..4b6669c7ed9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -829,7 +829,10 @@ vec4_visitor::run()
}
}
- reg_allocate();
+ while (!reg_allocate()) {
+ if (failed)
+ break;
+ }
if (failed)
return false;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 11c97a919d2..0402d3b3034 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -41,7 +41,7 @@ assign(unsigned int *reg_hw_locations, reg *reg)
}
}
-void
+bool
vec4_visitor::reg_allocate_trivial()
{
unsigned int hw_reg_mapping[this->virtual_grf_count];
@@ -90,7 +90,10 @@ vec4_visitor::reg_allocate_trivial()
if (prog_data->total_grf > max_grf) {
fail("Ran out of regs on trivial allocator (%d/%d)\n",
prog_data->total_grf, max_grf);
+ return false;
}
+
+ return true;
}
static void
@@ -139,7 +142,7 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
ra_set_finalize(brw->vs.regs);
}
-void
+bool
vec4_visitor::reg_allocate()
{
unsigned int hw_reg_mapping[virtual_grf_count];
@@ -151,10 +154,8 @@ vec4_visitor::reg_allocate()
/* Using the trivial allocator can be useful in debugging undefined
* register access as a result of broken optimization passes.
*/
- if (0) {
- reg_allocate_trivial();
- return;
- }
+ if (0)
+ return reg_allocate_trivial();
calculate_live_intervals();
@@ -213,7 +214,7 @@ vec4_visitor::reg_allocate()
spill_reg(reg);
}
ralloc_free(g);
- return;
+ return false;
}
/* Get the chosen virtual registers for each node, and map virtual
@@ -239,6 +240,8 @@ vec4_visitor::reg_allocate()
}
ralloc_free(g);
+
+ return true;
}
void