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| author | Rob Clark <robdclark@chromium.org> | 2019-05-31 07:07:57 -0700 |
|---|---|---|
| committer | Juan A. Suarez Romero <jasuarez@igalia.com> | 2019-06-04 15:06:46 +0000 |
| commit | 3fce389c8b7dad2179ff939d7be8dfe38454bee9 (patch) | |
| tree | f1f9fc977a1c690c66e4ef95e8c205b4eaa7995b | |
| parent | a37f10af7be93f87573b44de979dafd6821d5e59 (diff) | |
| download | mesa-3fce389c8b7dad2179ff939d7be8dfe38454bee9.tar.gz | |
freedreno/a6xx: fix GPU crash on small render targets
Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 8eaa2d502131bdce874603f522eabc4a5719f2e6)
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index a00e4446333..6ad0bc68ef4 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -640,6 +640,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring) blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx); blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy); + /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for + * small render targets. But since we align pitch to binw I think + * we can get away avoiding GPU hangs a simpler way, by just rounding + * up the blit scissor: + */ + blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw); + OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2); OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) | |