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| author | Anuj Phogat <anuj.phogat@gmail.com> | 2019-01-24 14:46:02 -0800 |
|---|---|---|
| committer | Anuj Phogat <anuj.phogat@gmail.com> | 2019-03-12 16:20:19 -0700 |
| commit | e78e3a1ee2f5214f94596a277560237c7aab40ba (patch) | |
| tree | 2eec565c3fd059e6d268ac1a156d30272d34fa3f | |
| parent | fc1b70aeac8251ffb4c78eb7b4d016f80214a117 (diff) | |
| download | mesa-icl_wa_2204188704.tar.gz | |
anv/icl: Add WA_2204188704 to disable pixel shader panic dispatchicl_wa_2204188704
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
| -rw-r--r-- | src/intel/genxml/gen11.xml | 5 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 12 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index a7c06c5ab60..6f3aba46561 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3681,4 +3681,9 @@ <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/> </register> + <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304"> + <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/> + <field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/> + </register> + </genxml> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index cffd1e47247..6d55e5dc5c6 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -200,6 +200,18 @@ genX(init_device_state)(struct anv_device *device) lri.DataDWord = half_slice_chicken7; } + /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. + */ + uint32_t common_slice_chicken3; + anv_pack_struct(&common_slice_chicken3, GENX(COMMON_SLICE_CHICKEN3), + .PSThreadPanicDispatch = 0x3, + .PSThreadPanicDispatchMask = 0x3); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN3_num); + lri.DataDWord = common_slice_chicken3; + } + #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so |