| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Do not print warnings on stdout | Michael Müller | 2015-03-05 | 1 | -1/+1 |
| * | Add new debug option for aub dump | Zhenyu Wang | 2014-12-29 | 1 | -0/+1 |
| * | Add the override flag to assure that HEVC video command always uses BSD ring0... | Zhao Yakui | 2014-12-14 | 1 | -0/+1 |
| * | HEVC: gen9_hcpd_ref_idx_state() | Xiang, Haihao | 2014-12-14 | 1 | -0/+1 |
| * | Skl: Add the PCIIDs and initial driver-codec info for Skl | Zhao Yakui | 2014-12-14 | 1 | -0/+2 |
| * | CHV: Add PCIID placeholders for CHV | Sean V Kelley | 2014-09-30 | 1 | -0/+2 |
| * | debug: add g_intel_debug_option_flags for simple driver debug | Zhao, Halley | 2014-06-06 | 1 | -2/+7 |
| * | Simplify some macros | Xiang, Haihao | 2014-05-26 | 1 | -266/+10 |
| * | Add a new intel_device_info structure | Xiang, Haihao | 2014-05-26 | 1 | -0/+16 |
| * | clean up some assert in i965_drv_video.c | Zhao, Halley | 2014-04-23 | 1 | -0/+7 |
| * | va: User specified tiling and stride support. | Zhao, Halley | 2014-04-23 | 1 | -0/+1 |
| * | New PCI IDs for BDW | Xiang, Haihao | 2014-02-27 | 1 | -3/+10 |
| * | Initialize the 8x8 sampler for AVS on BDW | Zhao Yakui | 2014-02-27 | 1 | -0/+2 |
| * | Add the PCI ids for BDW | Zhao Yakui | 2014-02-27 | 1 | -0/+43 |
| * | Workaround for SNB | Xiang, Haihao | 2013-11-13 | 1 | -0/+2 |
| * | Enable the Bay Trail platform. | Zhao Halley | 2013-09-06 | 1 | -1/+17 |
| * | Check whether VEBOX is supported by the underlying OS | Xiang, Haihao | 2013-07-01 | 1 | -0/+1 |
| * | Revert "Make it built against the current upstream libdrm" | Xiang, Haihao | 2013-06-25 | 1 | -4/+0 |
| * | More reserved PCI IDs for Haswell | Xiang, Haihao | 2013-06-09 | 1 | -3/+53 |
| * | Fix Haswell GT3 | Xiang, Haihao | 2013-06-09 | 1 | -26/+28 |
| * | Merge branch 'master' into staging | Xiang, Haihao | 2013-04-03 | 1 | -0/+1 |
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| | * | Update PCI IDs for Haswell CRW | Xiang, Haihao | 2013-03-04 | 1 | -9/+9 |
| | * | Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_... | Xiang, Haihao | 2012-12-28 | 1 | -46/+52 |
| | * | VPP: Render target surface with background color | Xiang, Haihao | 2012-10-31 | 1 | -0/+2 |
| | * | Make it built against the current upstream libdrm | Xiang, Haihao | 2012-10-24 | 1 | -0/+4 |
| | * | Handle the MFX change between A stepping and B-stepping for haswell | Zhao Yakui | 2012-10-23 | 1 | -0/+1 |
| | * | Add haswell PCI IDs | Gwenole Beauchesne | 2012-10-23 | 1 | -1/+87 |
| | * | Fix build with VA-API 0.32.0. | Gwenole Beauchesne | 2012-10-08 | 1 | -0/+1 |
| | * | Add support for new Ivybridge chipset | Xiang, Haihao | 2012-04-13 | 1 | -1/+3 |
| | * | Add WARN_ONCE() helper macro. | Gwenole Beauchesne | 2012-03-18 | 1 | -0/+8 |
| * | | Fix the initilization path and the termination path in reverse | Xiang, Haihao | 2013-03-15 | 1 | -2/+3 |
| * | | Update PCI IDs for Haswell CRW | Xiang, Haihao | 2013-03-04 | 1 | -9/+9 |
| * | | Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_... | Xiang, Haihao | 2012-12-28 | 1 | -46/+52 |
| * | | Make it built against the current upstream libdrm | Xiang, Haihao | 2012-10-29 | 1 | -0/+4 |
| * | | Handle the MFX change between A stepping and B-stepping for haswell | Zhao Yakui | 2012-10-23 | 1 | -0/+1 |
| * | | Add PCI IDs for Haswell | Gwenole Beauchesne | 2012-10-23 | 1 | -1/+87 |
| * | | Add support for new Ivybridge chipset | Xiang, Haihao | 2012-04-13 | 1 | -1/+3 |
| * | | Add WARN_ONCE() helper macro. | Gwenole Beauchesne | 2012-03-29 | 1 | -0/+8 |
| * | | Clear target surface with specified color | Xiang, Haihao | 2012-01-30 | 1 | -0/+2 |
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| * | Avoid depending on va_backend.h for some files | Xiang, Haihao | 2012-01-10 | 1 | -0/+5 |
| * | Remove legacy DRI support | Xiang, Haihao | 2012-01-10 | 1 | -6/+0 |
| * | Add support for B43 chipset | Xiang, Haihao | 2011-12-07 | 1 | -1/+6 |
| * | Moved files around. | Gwenole Beauchesne | 2011-08-22 | 1 | -0/+186 |
