Unify the coding style in the driver

Linux coding style is used in the driver source code. Use the command
below to format/indent .c/.h files

$> astyle --style=linux -cnpUH -s4 -M120 <file>

A script of style_unify is added in the top-level directory to
handle all .c/.h files in the driver. There is no change to any
functionality

This fixes https://github.com/01org/intel-vaapi-driver/issues/99

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

1 files changed, 93 insertions, 93 deletions

diff --git a/src/gen9_render.c b/src/gen9_render.c
index 4c244433..b609fea5 100644
--- a/src/gen9_render.c
+++ b/src/gen9_render.c
@@ -50,7 +50,7 @@
 #include "i965_render.h"
 
 /* Programs for Gen8 */
-static const uint32_t sf_kernel_static_gen9[][4] ={
+static const uint32_t sf_kernel_static_gen9[][4] = {
 
 };
 static const uint32_t ps_kernel_static_gen9[][4] = {
@@ -104,38 +104,38 @@ static struct i965_kernel render_kernels_gen9[] = {
     }
 };
 
-#define URB_VS_ENTRIES	      8
+#define URB_VS_ENTRIES        8
 #define URB_VS_ENTRY_SIZE     1
 
-#define URB_GS_ENTRIES	      0
+#define URB_GS_ENTRIES        0
 #define URB_GS_ENTRY_SIZE     0
 
 #define URB_CLIP_ENTRIES      0
 #define URB_CLIP_ENTRY_SIZE   0
 
-#define URB_SF_ENTRIES	      1
+#define URB_SF_ENTRIES        1
 #define URB_SF_ENTRY_SIZE     2
 
-#define URB_CS_ENTRIES	      4
+#define URB_CS_ENTRIES        4
 #define URB_CS_ENTRY_SIZE     4
 
 static void
 gen9_render_set_surface_tiling(struct gen8_surface_state *ss, uint32_t tiling)
 {
-   switch (tiling) {
-   case I915_TILING_NONE:
-      ss->ss0.tiled_surface = 0;
-      ss->ss0.tile_walk = 0;
-      break;
-   case I915_TILING_X:
-      ss->ss0.tiled_surface = 1;
-      ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
-      break;
-   case I915_TILING_Y:
-      ss->ss0.tiled_surface = 1;
-      ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
-      break;
-   }
+    switch (tiling) {
+    case I915_TILING_NONE:
+        ss->ss0.tiled_surface = 0;
+        ss->ss0.tile_walk = 0;
+        break;
+    case I915_TILING_X:
+        ss->ss0.tiled_surface = 1;
+        ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
+        break;
+    case I915_TILING_Y:
+        ss->ss0.tiled_surface = 1;
+        ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
+        break;
+    }
 }
 
 /* Set "Shader Channel Select" for GEN9+ */
@@ -165,7 +165,7 @@ gen9_render_set_surface_state(
 
     memset(ss, 0, sizeof(*ss));
 
-    switch (flags & (VA_TOP_FIELD|VA_BOTTOM_FIELD)) {
+    switch (flags & (VA_TOP_FIELD | VA_BOTTOM_FIELD)) {
     case VA_BOTTOM_FIELD:
         ss->ss0.vert_line_stride_ofs = 1;
         /* fall-through */
@@ -323,9 +323,9 @@ gen9_render_dest_surface_state(VADriverContextP ctx, int index)
     assert(index < MAX_RENDER_SURFACES);
 
     if (dest_region->cpp == 2) {
-	format = I965_SURFACEFORMAT_B5G6R5_UNORM;
+        format = I965_SURFACEFORMAT_B5G6R5_UNORM;
     } else {
-	format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
+        format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
     }
 
     dri_bo_map(ss_bo, 1);
@@ -585,19 +585,19 @@ gen9_render_initialize(VADriverContextP ctx)
     render_state->cc_viewport_size = sizeof(struct i965_cc_viewport);
 
     render_state->blend_state_size = sizeof(struct gen8_global_blend_state) +
-			16 * sizeof(struct gen8_blend_state_rt);
+                                     16 * sizeof(struct gen8_blend_state_rt);
 
     render_state->sf_clip_size = 1024;
 
     render_state->scissor_size = 1024;
 
     size = ALIGN(render_state->curbe_size, ALIGNMENT) +
-        ALIGN(render_state->sampler_size, ALIGNMENT) +
-        ALIGN(render_state->cc_viewport_size, ALIGNMENT) +
-        ALIGN(render_state->cc_state_size, ALIGNMENT) +
-        ALIGN(render_state->blend_state_size, ALIGNMENT) +
-        ALIGN(render_state->sf_clip_size, ALIGNMENT) +
-        ALIGN(render_state->scissor_size, ALIGNMENT);
+           ALIGN(render_state->sampler_size, ALIGNMENT) +
+           ALIGN(render_state->cc_viewport_size, ALIGNMENT) +
+           ALIGN(render_state->cc_state_size, ALIGNMENT) +
+           ALIGN(render_state->blend_state_size, ALIGNMENT) +
+           ALIGN(render_state->sf_clip_size, ALIGNMENT) +
+           ALIGN(render_state->scissor_size, ALIGNMENT);
 
     dri_bo_unreference(render_state->dynamic_state.bo);
     bo = dri_bo_alloc(i965->intel.bufmgr,
@@ -659,7 +659,7 @@ gen9_render_sampler(VADriverContextP ctx)
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->sampler_offset;
+             render_state->sampler_offset;
 
     sampler_state = (struct gen8_sampler_state *) cc_ptr;
 
@@ -689,7 +689,7 @@ gen9_render_blend_state(VADriverContextP ctx)
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->blend_state_offset;
+             render_state->blend_state_offset;
 
     global_blend_state = (struct gen8_global_blend_state*) cc_ptr;
 
@@ -716,7 +716,7 @@ gen9_render_cc_viewport(VADriverContextP ctx)
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->cc_viewport_offset;
+             render_state->cc_viewport_offset;
 
     cc_viewport = (struct i965_cc_viewport *) cc_ptr;
 
@@ -740,7 +740,7 @@ gen9_render_color_calc_state(VADriverContextP ctx)
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->cc_state_offset;
+             render_state->cc_state_offset;
 
     color_calc_state = (struct gen6_color_calc_state *) cc_ptr;
 
@@ -777,7 +777,7 @@ gen9_render_upload_constants(VADriverContextP ctx,
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->curbe_offset;
+             render_state->curbe_offset;
 
     constant_buffer = (unsigned short *) cc_ptr;
 
@@ -846,28 +846,28 @@ gen9_emit_state_base_address(VADriverContextP ctx)
     BEGIN_BATCH(batch, 19);
     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (19 - 2));
     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
-	OUT_BATCH(batch, 0);
-	OUT_BATCH(batch, 0);
-	/*DW4 */
+    OUT_BATCH(batch, 0);
+    OUT_BATCH(batch, 0);
+    /*DW4 */
     OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
-	OUT_BATCH(batch, 0);
+    OUT_BATCH(batch, 0);
 
-	/*DW6*/
+    /*DW6*/
     /* Dynamic state base address */
     OUT_RELOC(batch, render_state->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
-		0, BASE_ADDRESS_MODIFY);
+              0, BASE_ADDRESS_MODIFY);
     OUT_BATCH(batch, 0);
 
-	/*DW8*/
+    /*DW8*/
     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
     OUT_BATCH(batch, 0);
 
-	/*DW10 */
+    /*DW10 */
     /* Instruction base address */
     OUT_RELOC(batch, render_state->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
     OUT_BATCH(batch, 0);
 
-	/*DW12 */
+    /*DW12 */
     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* General state upper bound */
     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
@@ -910,7 +910,7 @@ gen9_emit_vertices(VADriverContextP ctx)
     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
     OUT_BATCH(batch,
               (0 << GEN8_VB0_BUFFER_INDEX_SHIFT) |
-	      (0 << GEN8_VB0_MOCS_SHIFT) |
+              (0 << GEN8_VB0_MOCS_SHIFT) |
               GEN7_VB0_ADDRESS_MODIFYENABLE |
               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
@@ -983,7 +983,7 @@ gen9_emit_vertex_element_state(VADriverContextP ctx)
               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
               (8 << VE0_OFFSET_SHIFT));
     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-	      (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+              (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
 
@@ -1096,8 +1096,8 @@ gen9_emit_urb(VADriverContextP ctx)
     OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
     /* Size is 8Kbs and base address is 0Kb */
     OUT_BATCH(batch,
-		(0 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) |
-		(8 << GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT));
+              (0 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) |
+              (8 << GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT));
     ADVANCE_BATCH(batch);
 
     BEGIN_BATCH(batch, 2);
@@ -1106,28 +1106,28 @@ gen9_emit_urb(VADriverContextP ctx)
               (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
               (4 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
               (4 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH(batch);
-
-   BEGIN_BATCH(batch, 2);
-   OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
-   OUT_BATCH(batch,
-             (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (5 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH(batch);
-
-   BEGIN_BATCH(batch, 2);
-   OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
-   OUT_BATCH(batch,
-             (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (6 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH(batch);
-
-   BEGIN_BATCH(batch, 2);
-   OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
-   OUT_BATCH(batch,
-             (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (7 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH(batch);
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
+    OUT_BATCH(batch,
+              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+              (5 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
+    OUT_BATCH(batch,
+              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+              (6 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
+    OUT_BATCH(batch,
+              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+              (7 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+    ADVANCE_BATCH(batch);
 }
 
 static void
@@ -1288,7 +1288,7 @@ gen9_emit_invarient_states(VADriverContextP ctx)
 
     BEGIN_BATCH(batch, 1);
     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D |
-                     GEN9_PIPELINE_SELECTION_MASK);
+              GEN9_PIPELINE_SELECTION_MASK);
     ADVANCE_BATCH(batch);
 
     BEGIN_BATCH(batch, 2);
@@ -1354,8 +1354,8 @@ gen9_emit_sf_state(VADriverContextP ctx)
     BEGIN_BATCH(batch, 6);
     OUT_BATCH(batch, GEN7_3DSTATE_SBE | (6 - 2));
     OUT_BATCH(batch,
-	      (GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH) |
-	      (GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET) |
+              (GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH) |
+              (GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET) |
               (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
               (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
               (1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
@@ -1406,22 +1406,22 @@ gen9_emit_wm_state(VADriverContextP ctx, int kernel)
     ADVANCE_BATCH(batch);
 
     if (kernel == PS_KERNEL) {
-	BEGIN_BATCH(batch, 2);
-	OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
-	OUT_BATCH(batch,
-		GEN8_PS_BLEND_HAS_WRITEABLE_RT);
-	ADVANCE_BATCH(batch);
+        BEGIN_BATCH(batch, 2);
+        OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
+        OUT_BATCH(batch,
+                  GEN8_PS_BLEND_HAS_WRITEABLE_RT);
+        ADVANCE_BATCH(batch);
     } else if (kernel == PS_SUBPIC_KERNEL) {
-	BEGIN_BATCH(batch, 2);
-	OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
-	OUT_BATCH(batch,
-		(GEN8_PS_BLEND_HAS_WRITEABLE_RT |
-		 GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE |
-		 (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT) |
-		 (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT) |
-		 (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT) |
-		 (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT)));
-	ADVANCE_BATCH(batch);
+        BEGIN_BATCH(batch, 2);
+        OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
+        OUT_BATCH(batch,
+                  (GEN8_PS_BLEND_HAS_WRITEABLE_RT |
+                   GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE |
+                   (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT) |
+                   (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT) |
+                   (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT) |
+                   (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT)));
+        ADVANCE_BATCH(batch);
     }
 
     BEGIN_BATCH(batch, 2);
@@ -1653,7 +1653,7 @@ gen9_subpicture_render_blend_state(VADriverContextP ctx)
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-			render_state->blend_state_offset;
+             render_state->blend_state_offset;
 
     global_blend_state = (struct gen8_global_blend_state*) cc_ptr;
 
@@ -1695,7 +1695,7 @@ gen9_subpic_render_upload_constants(VADriverContextP ctx,
     assert(render_state->dynamic_state.bo->virtual);
 
     cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
-				render_state->curbe_offset;
+             render_state->curbe_offset;
 
     constant_buffer = (float *) cc_ptr;
     *constant_buffer = global_alpha;
@@ -1791,7 +1791,7 @@ gen9_render_init(VADriverContextP ctx)
     render_state->render_terminate = gen9_render_terminate;
 
     memcpy(render_state->render_kernels, render_kernels_gen9,
-			sizeof(render_state->render_kernels));
+           sizeof(render_state->render_kernels));
 
     kernel_size = 4096;
 
@@ -1805,9 +1805,9 @@ gen9_render_init(VADriverContextP ctx)
     }
 
     render_state->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr,
-                                  "kernel shader",
-                                  kernel_size,
-                                  0x1000);
+                                                      "kernel shader",
+                                                      kernel_size,
+                                                      0x1000);
     if (render_state->instruction_state.bo == NULL) {
         WARN_ONCE("failure to allocate the buffer space for kernel shader\n");
         return false;