| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64]Remove be_checked_get_lane, check bounds with __builtin_aarch64_im_l... | alalaw01 | 2014-12-09 | 1 | -3/+0 |
| * | [AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsi | alalaw01 | 2014-12-09 | 1 | -2/+0 |
| * | * config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite using | fyang | 2014-12-08 | 1 | -0/+8 |
| * | * config/aarch64/aarch64-simd.md (clrsb<mode>2, popcount<mode>2): New | fyang | 2014-12-07 | 1 | -0/+2 |
| * | 2014-12-05 Andrew Pinski <apinski@cavium.com> | pinskia | 2014-12-05 | 1 | -1/+1 |
| * | [AArch64] Remove/merge redundant iterators | alalaw01 | 2014-12-03 | 1 | -14/+14 |
| * | [AArch64] Add vector pattern for __builtin_ctz | jiwang | 2014-11-21 | 1 | -0/+1 |
| * | gcc/: | alalaw01 | 2014-11-17 | 1 | -1/+0 |
| * | Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips ... | alalaw01 | 2014-11-12 | 1 | -32/+34 |
| * | [AArch64] Use new reduc_[us](min|max)_scal optabs, inc. for builtins | alalaw01 | 2014-10-27 | 1 | -7/+7 |
| * | [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins | alalaw01 | 2014-10-27 | 1 | -3/+2 |
| * | [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in... | cbaylis | 2014-10-24 | 1 | -0/+4 |
| * | PR target/63173 | fyang | 2014-10-24 | 1 | -0/+4 |
| * | [AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32 | jgreenhalgh | 2014-09-30 | 1 | -1/+1 |
| * | [AArch64] Simplify vreinterpret for float64x1_t using casts. | alalaw01 | 2014-09-11 | 1 | -23/+0 |
| * | [AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la... | ktkachov | 2014-09-09 | 1 | -8/+8 |
| * | [PATCH AArch64 2/2] Remove vector compare/tst __builtins | alalaw01 | 2014-09-05 | 1 | -11/+0 |
| * | [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction | alalaw01 | 2014-09-05 | 1 | -1/+1 |
| * | [PATCH AArch64] Add a builtin for rbit(q?)_p8; add intrinsics and tests. | alalaw01 | 2014-09-05 | 1 | -0/+2 |
| * | [AArch64] Implement some saturating math NEON intrinsics. | ktkachov | 2014-08-05 | 1 | -2/+2 |
| * | Removed unused get_lane and dup_lane builtins. | alalaw01 | 2014-08-01 | 1 | -3/+0 |
| * | PR/60825 Make {int,uint}64x1_t in arm_neon.h a proper vector type | alalaw01 | 2014-06-23 | 1 | -0/+2 |
| * | PR/60825 Make float64x1_t in arm_neon.h a proper vector type | alalaw01 | 2014-06-23 | 1 | -19/+19 |
| * | [PATCH AArch64 2/2] Correct signedness of builtins, remove casts from arm_neon.h | alalaw01 | 2014-06-03 | 1 | -5/+5 |
| * | [PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h | alalaw01 | 2014-06-03 | 1 | -13/+13 |
| * | Detect EXT patterns to vec_perm_const, use for EXT intrinsics | alalaw01 | 2014-05-29 | 1 | -0/+3 |
| * | [AArch64] Improve vst4_lane intrinsics | jgreenhalgh | 2014-04-28 | 1 | -0/+4 |
| * | [AArch64] Vectorise bswap[16,32,64] | ktkachov | 2014-04-24 | 1 | -0/+2 |
| * | [AArch64] 64-bit float vreinterpret implemention | mshawcroft | 2014-04-22 | 1 | -0/+22 |
| * | [AArch64] Vreinterpret re-implemention. | mshawcroft | 2014-04-22 | 1 | -11/+0 |
| * | [AArch64] vqneg and vqabs intrinsics implementation. | mshawcroft | 2014-04-22 | 1 | -2/+2 |
| * | [AArch64] vrnd<*>_f64 patch | mshawcroft | 2014-04-22 | 1 | -1/+1 |
| * | [AArch64] Logical vector shift right conformance | jgreenhalgh | 2014-03-24 | 1 | -1/+2 |
| * | [PATCH][AArch64] Vector shift by 64 fix | jgreenhalgh | 2014-01-23 | 1 | -1/+2 |
| * | [AArch64_BE 2/4] Big-Endian lane numbering fix | ktkachov | 2014-01-23 | 1 | -0/+1 |
| * | Update copyright years in gcc/ | rsandifo | 2014-01-02 | 1 | -1/+1 |
| * | Implement support for AArch64 Crypto PMULL.64. | belagod | 2013-12-19 | 1 | -0/+4 |
| * | Implement support for AArch64 Crypto SHA256. | belagod | 2013-12-19 | 1 | -0/+6 |
| * | Implement support for AArch64 Crypto SHA1. | belagod | 2013-12-19 | 1 | -0/+8 |
| * | Implement support for AArch64 Crypto AES. | belagod | 2013-12-19 | 1 | -0/+5 |
| * | [AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins | jgreenhalgh | 2013-11-26 | 1 | -0/+5 |
| * | [AArch64] Implement vclz ADVSimd intrinsic. | mshawcroft | 2013-10-09 | 1 | -1/+1 |
| * | [AArch64] Improve arm_neon.h vml<as>_lane handling. | jgreenhalgh | 2013-09-16 | 1 | -0/+3 |
| * | [AArch64] Fixup the vget_lane RTL patterns and intrinsics | jgreenhalgh | 2013-08-09 | 1 | -5/+3 |
| * | [AArch64] Rewrite vabs<q>_s<8,16,32,64> AdvSIMD intrinsics to fold to tree | jgreenhalgh | 2013-07-20 | 1 | -1/+1 |
| * | [AArch64] Convert ld1, st1 arm_neon.h intrinsics to RTL builtins. | jgreenhalgh | 2013-07-03 | 1 | -0/+7 |
| * | gcc/ | sofiane | 2013-06-17 | 1 | -1/+1 |
| * | [AArch64] Support for CLZ | mshawcroft | 2013-05-23 | 1 | -0/+1 |
| * | [AArch64] Refactor reduc_<su>plus patterns. | jgreenhalgh | 2013-05-01 | 1 | -2/+3 |
| * | [AArch64] Refactor vector max and min RTL and builtins. | jgreenhalgh | 2013-05-01 | 1 | -7/+15 |
