PR/60825 Make float64x1_t in arm_neon.h a proper vector type

gcc/ChangeLog:
	PR target/60825
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
	V1DFmode.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):
	add V1DFmode
	(BUILTIN_VD1): New.
	(BUILTIN_VD_RE): Remove.
	(aarch64_init_simd_builtins): Add V1DF to modes/modenames.
	(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.
	* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df
	variant but not df.
	(vreinterpretv1df*, vreinterpret*v1df): New.
	(vreinterpretdf*, vreinterpret*df): Remove.
	* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):
	Generate V1DFmode pattern not DFmode.
	* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.
	(VD1): New.
	* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.
	(vcreate_f64): Remove cast, use v1df builtin.
	(vcombine_f64): Remove cast, get elements with gcc vector extensions.
	(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,
	vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,
	vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,
	vmov_n_f64, vst1_f64): Use gcc vector extensions.
	(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,
	add range check using __builtin_aarch64_im_lane_boundsi.
	(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,
	vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix
	type signature, use gcc vector extensions.
	(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,
	vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,
	vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,
	vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,
	vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,
	vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,
	vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,
	vreinterpret_u64_f64): Use v1df builtin not df.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
	* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
	* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.
	* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.
	* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.
	* gcc.target/aarch64/vsub_f64.c: Likewise.
	* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme
	as now the same for all variants.
	* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not
	float64x1_t.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211892 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 19 insertions, 19 deletions

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index faa0858e3be..1b931bede94 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -39,7 +39,7 @@
    1-9 - CODE_FOR_<name><mode><1-9>
    10 - CODE_FOR_<name><mode>.  */
 
-  BUILTIN_VD_RE (CREATE, create, 0)
+  BUILTIN_VD1 (CREATE, create, 0)
   BUILTIN_VDC (COMBINE, combine, 0)
   BUILTIN_VB (BINOP, pmul, 0)
   BUILTIN_VDQF (UNOP, sqrt, 2)
@@ -51,28 +51,28 @@
   VAR1 (GETLANE, get_lane, 0, di)
   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
 
-  VAR1 (REINTERP_SS, reinterpretdi, 0, df)
-  VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
-  VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
-  VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
-  VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
-  BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
+  VAR1 (REINTERP_SS, reinterpretdi, 0, v1df)
+  VAR1 (REINTERP_SS, reinterpretv8qi, 0, v1df)
+  VAR1 (REINTERP_SS, reinterpretv4hi, 0, v1df)
+  VAR1 (REINTERP_SS, reinterpretv2si, 0, v1df)
+  VAR1 (REINTERP_SS, reinterpretv2sf, 0, v1df)
+  BUILTIN_VD (REINTERP_SS, reinterpretv1df, 0)
 
-  BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
+  BUILTIN_VD (REINTERP_SU, reinterpretv1df, 0)
 
-  VAR1 (REINTERP_US, reinterpretdi, 0, df)
-  VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
-  VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
-  VAR1 (REINTERP_US, reinterpretv2si, 0, df)
-  VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
+  VAR1 (REINTERP_US, reinterpretdi, 0, v1df)
+  VAR1 (REINTERP_US, reinterpretv8qi, 0, v1df)
+  VAR1 (REINTERP_US, reinterpretv4hi, 0, v1df)
+  VAR1 (REINTERP_US, reinterpretv2si, 0, v1df)
+  VAR1 (REINTERP_US, reinterpretv2sf, 0, v1df)
 
-  BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
+  BUILTIN_VD (REINTERP_SP, reinterpretv1df, 0)
 
-  VAR1 (REINTERP_PS, reinterpretdi, 0, df)
-  VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
-  VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
-  VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
-  VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
+  VAR1 (REINTERP_PS, reinterpretdi, 0, v1df)
+  VAR1 (REINTERP_PS, reinterpretv8qi, 0, v1df)
+  VAR1 (REINTERP_PS, reinterpretv4hi, 0, v1df)
+  VAR1 (REINTERP_PS, reinterpretv2si, 0, v1df)
+  VAR1 (REINTERP_PS, reinterpretv2sf, 0, v1df)
 
   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */