diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c new file mode 100644 index 00000000000..a707aa1645e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n, int m) +{ + for (int i = 0; i < n; i++) { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); + } + + for (int i = 0; i < n; i++) { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RNE, 4); + __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4); + } +} + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 1 } } */ |