RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions

Hi, this patch support the new coming fixed-point intrinsics:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

Insert fixed-point rounding mode configuration by mode switching target hook.

Mode switching target hook is implemented applying LCM (Lazy code Motion).

So the performance && correctness can be well trusted.

Here is the example:

void f (void * in, void *out, int32_t x, int n, int m)
{
  for (int i = 0; i < n; i++) {
    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
    __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
  }

  for (int i = 0; i < n; i++) {
    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
    __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
  }
}

ASM:

...
csrwi   vxrm,2
vsetivli        zero,4,e32,m1,tu,ma
...
Loop 1
...
Loop 2

mode switching can global recognize both Loop 1 and Loop 2 are using RDN
rounding mode and hoist such single "csrwi vxrm,2" to dominate both Loop 1
and Loop 2.

Besides, I have add correctness check sanity tests in this patch too.

Ok for trunk ?

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum riscv_entity): New enum.
	* config/riscv/riscv.cc (riscv_emit_mode_set): New function.
	(riscv_mode_needed): Ditto.
	(riscv_mode_after): Ditto.
	(riscv_mode_entry): Ditto.
	(riscv_mode_exit): Ditto.
	(riscv_mode_priority): Ditto.
	(TARGET_MODE_EMIT): New target hook.
	(TARGET_MODE_NEEDED): Ditto.
	(TARGET_MODE_AFTER): Ditto.
	(TARGET_MODE_ENTRY): Ditto.
	(TARGET_MODE_EXIT): Ditto.
	(TARGET_MODE_PRIORITY): Ditto.
	* config/riscv/riscv.h (OPTIMIZE_MODE_SWITCHING): Ditto.
	(NUM_MODES_FOR_MODE_SWITCHING): Ditto.
	* config/riscv/riscv.md: Add csrwvxrm.
	* config/riscv/vector.md (rnu,rne,rdn,rod,none): New attribute.
	(vxrmsi): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vxrm-10.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-6.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-7.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-8.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-9.c: New test.

1 files changed, 26 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
new file mode 100644
index 00000000000..a707aa1645e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-10.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * in, void *out, int32_t x, int n, int m)
+{
+  for (int i = 0; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
+  }
+  
+  for (int i = 0; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 1000, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i + 1000, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RNE, 4);
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RNE, 4);
+    __riscv_vse32_v_i32m1 (out + 100 + i + 1000, v3, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*1} 1 } } */
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 1 } } */