1 files changed, 18 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
new file mode 100644
index 00000000000..96a0387fce5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
@@ -0,0 +1,18 @@
+/* { dg-options "-fno-common isa_rev<=5" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */
+/* { dg-final { scan-assembler-not "\tmemcpy" } } */
+/* { dg-final { scan-assembler-times "swl" 8 } } */
+/* { dg-final { scan-assembler-times "swr" 8 } } */
+
+/* Test that inline memcpy for hardware with swl, swr handles subword
+   alignment and produces enough swl/swrs for mips32.  */
+
+#include <string.h>
+
+char c[40] __attribute__ ((aligned(2)));
+
+void
+f1 ()
+{
+  memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32);
+}