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| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:20:51 +0000 |
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| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:20:51 +0000 |
| commit | 2d9d01985a7a7866916fafa19c5c296702e69714 (patch) | |
| tree | 259c095c65fc0c6279b7a17755b3f851f51babb3 /gcc/testsuite/gcc.target/mips/inline-memcpy-3.c | |
| parent | c8ebeb0e3c6b093e649592be7d51d1c0032a1dc7 (diff) | |
| download | gcc-2d9d01985a7a7866916fafa19c5c296702e69714.tar.gz | |
2016-02-10 Basile Starynkevitch <basile@starynkevitch.net>
{{merging with even more of GCC 6, using subversion 1.9
svn merge -r227001:227400 ^/trunk ;
there is some gengtype issue before svn r228000... }}
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@233281 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target/mips/inline-memcpy-3.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/inline-memcpy-3.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c new file mode 100644 index 00000000000..96a0387fce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c @@ -0,0 +1,18 @@ +/* { dg-options "-fno-common isa_rev<=5" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ +/* { dg-final { scan-assembler-times "swl" 8 } } */ +/* { dg-final { scan-assembler-times "swr" 8 } } */ + +/* Test that inline memcpy for hardware with swl, swr handles subword + alignment and produces enough swl/swrs for mips32. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(2))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} |