diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/aarch64')
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ccmp_2.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/cmp-2.c | 21 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c | 53 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c | 49 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c | 45 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c | 52 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c | 59 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr63304_1.c | 18 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr79041-2.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr81414.C | 9 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c | 48 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c | 67 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/stack-checking.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c | 18 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c | 65 |
15 files changed, 495 insertions, 34 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_2.c b/gcc/testsuite/gcc.target/aarch64/ccmp_2.c new file mode 100644 index 00000000000..77ab0207886 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmp_2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int g(void); +int h(int a, _Bool c) +{ + if (a != 0 && c) + return g(); + return 1; +} + +/* { dg-final { scan-assembler "\tccmp\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/cmp-2.c b/gcc/testsuite/gcc.target/aarch64/cmp-2.c new file mode 100644 index 00000000000..12016647061 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmp-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int lt (int x, int y) +{ + if ((x - y) < 0) + return 10; + + return 0; +} + +int ge (int x, int y) +{ + if ((x - y) >= 0) + return 10; + + return 0; +} + +/* { dg-final { scan-assembler-times "csel\t" 2 } } */ +/* { dg-final { scan-assembler-not "sub\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c new file mode 100644 index 00000000000..e8dd01db056 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-skip-if "Tiny model won't generate adrp" { *-*-* } { "-mcmodel=tiny" } { "" } } */ + +double d0(void) +{ + double x = 0.0d; + return x; +} + +double dn1(void) +{ + double x = -0.0d; + return x; +} + + +double d1(void) +{ + double x = 1.5d; + return x; +} + +double d2(void) +{ + double x = 123256.0d; + return x; +} + +double d3(void) +{ + double x = 123256123456.0d; + return x; +} + +double d4(void) +{ + double x = 123456123456123456.0d; + return x; +} + +/* { dg-final { scan-assembler-times "movi\td\[0-9\]+, #?0" 1 } } */ + +/* { dg-final { scan-assembler-times "adrp\tx\[0-9\]+, \.LC\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "ldr\td\[0-9\]+, \\\[x\[0-9\], #:lo12:\.LC\[0-9\]\\\]" 2 } } */ + +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, 1\\\.5e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c new file mode 100644 index 00000000000..1ed3831e139 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +extern __fp16 foo (); +extern void bar (__fp16* x); + +void f1 () +{ + volatile __fp16 a = 17.0; +} + + +void f2 (__fp16 *a) +{ + *a = 17.0; +} + +void f3 () +{ + __fp16 b = foo (); + b = 17.0; + bar (&b); +} + +__fp16 f4 () +{ + __fp16 a = 0; + __fp16 b = 1; + __fp16 c = 2; + __fp16 d = 4; + + __fp16 z = a + b; + z = z + c; + z = z - d; + return z; +} + +__fp16 f5 () +{ + __fp16 a = 16; + bar (&a); + return a; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, #?19520" 3 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0xbc, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x4c, lsl 8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c new file mode 100644 index 00000000000..6f44821e9d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include <arm_fp16.h> + +float16_t f0(void) +{ + float16_t x = 0.0f; + return x; +} + +float16_t fn1(void) +{ + float16_t x = -0.0f; + return x; +} + +float16_t f1(void) +{ + float16_t x = 256.0f; + return x; +} + +float16_t f2(void) +{ + float16_t x = 123256.0f; + return x; +} + +float16_t f3(void) +{ + float16_t x = 17.0; + return x; +} + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.4h, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x5c, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x7c, lsl 8" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 19520" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\th\[0-9\], w\[0-9\]+" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c new file mode 100644 index 00000000000..7b92a5ae40f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +float f0(void) +{ + float x = 0.0f; + return x; +} + +float fn1(void) +{ + float x = -0.0f; + return x; +} + +float f1(void) +{ + float x = 256.0f; + return x; +} + +float f2(void) +{ + float x = 123256.0f; + return x; +} + +float f3(void) +{ + float x = 2.0f; + return x; +} + +float f4(void) +{ + float x = -20000.1; + return x; +} + + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 48128" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0x47f0, lsl 16" 1 } } */ + +/* { dg-final { scan-assembler-times "fmov\ts\[0-9\]+, 2\\\.0e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 16435" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0xc69c, lsl 16" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c new file mode 100644 index 00000000000..6ac9065037f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3" } */ + +long long f1(void) +{ + return 0xffff6666; +} + +int f3(void) +{ + return 0xffff6666; +} + + +long f2(void) +{ + return 0x11110000ffff6666; +} + +long f4(void) +{ + return 0x11110001ffff6666; +} + +long f5(void) +{ + return 0x111100001ff6666; +} + +long f6(void) +{ + return 0x00001111ffff6666; +} + +long f7(void) +{ + return 0x000011116666ffff; +} + +long f8(void) +{ + return 0x0f0011116666ffff; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 4294927974" 3 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 1718026239" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -2576941057" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 26214" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0xf00, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 48" 2 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1000, lsl 32" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 32" 3 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x111, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1ff, lsl 16" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1, lsl 32" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c index c917f81c022..114d8c1a6c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c +++ b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c @@ -4,10 +4,10 @@ #pragma GCC target ("+nothing+simd, cmodel=small") int -cal (float a) +cal (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -19,11 +19,11 @@ cal (float a) #pragma GCC target ("cmodel=large") int -cal2 (float a) +cal2 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -33,11 +33,11 @@ cal2 (float a) #pragma GCC pop_options int -cal3 (float a) +cal3 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else diff --git a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c new file mode 100644 index 00000000000..a889dfdd895 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ +/* { dg-require-effective-target lp64 } */ + +__int128 +t (void) +{ + return (__int128)1 << 80; +} + +/* { dg-final { scan-assembler "adr" } } */ +/* { dg-final { scan-assembler-not "adrp" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr81414.C b/gcc/testsuite/gcc.target/aarch64/pr81414.C new file mode 100644 index 00000000000..53dfc7cf800 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr81414.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57" } */ + +typedef __Float32x2_t float32x2_t; +float32x2_t +foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) { + return __b * __c + __a; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c index 192bad9879b..8fd428115ba 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c @@ -7,12 +7,10 @@ extern void abort (); -#define CHECK(T, N, R, E) \ +#define CHECK(R, E) \ {\ - int i = 0;\ - for (; i < N; i++)\ - if (* (T *) &R[i] != * (T *) &E[i])\ - abort ();\ + if (__builtin_memcmp (&R, &E, sizeof (R)) != 0)\ + abort ();\ } int @@ -26,8 +24,8 @@ main (int argc, char **argv) float32x2_t f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); float32x2_t f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); - CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); - CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + CHECK (f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (f32x2_ret_maxnm, f32x2_exp_maxnm); /* v{min|max}nm_f32 NaN. */ f32x2_input1 = vdup_n_f32 (__builtin_nanf ("")); @@ -37,8 +35,8 @@ main (int argc, char **argv) f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); - CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); - CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + CHECK (f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (f32x2_ret_maxnm, f32x2_exp_maxnm); /* v{min|max}nmq_f32 normal. */ float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0); @@ -48,8 +46,8 @@ main (int argc, char **argv) float32x4_t f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); float32x4_t f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); - CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); - CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + CHECK (f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (f32x4_ret_maxnm, f32x4_exp_maxnm); /* v{min|max}nmq_f32 NaN. */ f32x4_input1 = vdupq_n_f32 (-__builtin_nanf ("")); @@ -59,8 +57,8 @@ main (int argc, char **argv) f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); - CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); - CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + CHECK (f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (f32x4_ret_maxnm, f32x4_exp_maxnm); /* v{min|max}nm_f64 normal. */ float64x1_t f64x1_input1 = vdup_n_f64 (1.23); @@ -69,16 +67,16 @@ main (int argc, char **argv) float64x1_t f64x1_exp_maxnm = vdup_n_f64 (4.56); float64x1_t f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); float64x1_t f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}_f64 normal. */ float64x1_t f64x1_exp_min = vdup_n_f64 (1.23); float64x1_t f64x1_exp_max = vdup_n_f64 (4.56); float64x1_t f64x1_ret_min = vmin_f64 (f64x1_input1, f64x1_input2); float64x1_t f64x1_ret_max = vmax_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_min, f64x1_exp_min); - CHECK (uint64_t, 1, f64x1_ret_max, f64x1_exp_max); + CHECK (f64x1_ret_min, f64x1_exp_min); + CHECK (f64x1_ret_max, f64x1_exp_max); /* v{min|max}nmq_f64 normal. */ float64x2_t f64x2_input1 = vdupq_n_f64 (1.23); @@ -87,8 +85,8 @@ main (int argc, char **argv) float64x2_t f64x2_exp_maxnm = vdupq_n_f64 (4.56); float64x2_t f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); float64x2_t f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); - CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); - CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + CHECK (f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (f64x2_ret_maxnm, f64x2_exp_maxnm); /* v{min|max}nm_f64 NaN. */ f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); @@ -98,8 +96,8 @@ main (int argc, char **argv) f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}_f64 NaN. */ f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); @@ -109,8 +107,8 @@ main (int argc, char **argv) f64x1_ret_minnm = vmin_f64 (f64x1_input1, f64x1_input2); f64x1_ret_maxnm = vmax_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}nmq_f64 NaN. */ f64x2_input1 = vdupq_n_f64 (-__builtin_nan ("")); @@ -120,8 +118,8 @@ main (int argc, char **argv) f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); - CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); - CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + CHECK (f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (f64x2_ret_maxnm, f64x2_exp_maxnm); return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c new file mode 100644 index 00000000000..df777581ab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +typedef short int __attribute__ ((vector_size (16))) v8hi; + +v8hi +mla8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + + +v8hi +mls8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef short int __attribute__ ((vector_size (8))) v4hi; + +v4hi +mla4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4hi +mls4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__ ((vector_size (16))) v4si; + +v4si +mla4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4si +mls4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__((vector_size (8))) v2si; + +v2si +mla2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v2si +mls2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} diff --git a/gcc/testsuite/gcc.target/aarch64/stack-checking.c b/gcc/testsuite/gcc.target/aarch64/stack-checking.c index 1d1530df62b..eaa40581c86 100644 --- a/gcc/testsuite/gcc.target/aarch64/stack-checking.c +++ b/gcc/testsuite/gcc.target/aarch64/stack-checking.c @@ -1,4 +1,5 @@ /* { dg-do run { target { *-*-linux* } } } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-fstack-check" } */ int main(void) diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c new file mode 100644 index 00000000000..33a2c0f45af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f (unsigned char *p) +{ + return p[0] == 50 || p[0] == 52; +} + +int +g (unsigned char *p) +{ + return (p[0] >> 4 & 0xfd) == 0; +} + +/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c new file mode 100644 index 00000000000..0bd326a879d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* The integer variable shift and rotate instructions truncate their + shift amounts by the datasize. Make sure that we don't emit a redundant + masking operation. */ + +unsigned +f1 (unsigned x, int y) +{ + return x << (y & 31); +} + +unsigned long long +f2 (unsigned long long x, int y) +{ + return x << (y & 63); +} + +unsigned long long +f3 (unsigned long long bit_addr, int y) +{ + unsigned long bitnumb = bit_addr & 63; + return (1LL << bitnumb); +} + +unsigned int +f4 (unsigned int x, unsigned int y) +{ + y &= 31; + return x >> y | (x << (32 - y)); +} + +unsigned long long +f5 (unsigned long long x, unsigned long long y) +{ + y &= 63; + return x >> y | (x << (64 - y)); +} + +unsigned int +f6 (unsigned int x, unsigned int y) +{ + return (x << (32 - (y & 31))); +} + +unsigned long long +f7 (unsigned long long x, unsigned long long y) +{ + return (x << (64 - (y & 63))); +} + +unsigned long long +f8 (unsigned long long x, unsigned long long y) +{ + return (x << -(y & 63)); +} + +/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */ +/* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-not "and\tw\[0-9\]+, w\[0-9\]+, 31" } } */ +/* { dg-final { scan-assembler-not "and\tx\[0-9\]+, x\[0-9\]+, 63" } } */ +/* { dg-final { scan-assembler-not "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ |