diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
309 files changed, 8194 insertions, 2405 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_2.c b/gcc/testsuite/gcc.target/aarch64/ccmp_2.c new file mode 100644 index 00000000000..77ab0207886 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmp_2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int g(void); +int h(int a, _Bool c) +{ + if (a != 0 && c) + return g(); + return 1; +} + +/* { dg-final { scan-assembler "\tccmp\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/cmp-2.c b/gcc/testsuite/gcc.target/aarch64/cmp-2.c new file mode 100644 index 00000000000..12016647061 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmp-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int lt (int x, int y) +{ + if ((x - y) < 0) + return 10; + + return 0; +} + +int ge (int x, int y) +{ + if ((x - y) >= 0) + return 10; + + return 0; +} + +/* { dg-final { scan-assembler-times "csel\t" 2 } } */ +/* { dg-final { scan-assembler-not "sub\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c new file mode 100644 index 00000000000..e8dd01db056 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-skip-if "Tiny model won't generate adrp" { *-*-* } { "-mcmodel=tiny" } { "" } } */ + +double d0(void) +{ + double x = 0.0d; + return x; +} + +double dn1(void) +{ + double x = -0.0d; + return x; +} + + +double d1(void) +{ + double x = 1.5d; + return x; +} + +double d2(void) +{ + double x = 123256.0d; + return x; +} + +double d3(void) +{ + double x = 123256123456.0d; + return x; +} + +double d4(void) +{ + double x = 123456123456123456.0d; + return x; +} + +/* { dg-final { scan-assembler-times "movi\td\[0-9\]+, #?0" 1 } } */ + +/* { dg-final { scan-assembler-times "adrp\tx\[0-9\]+, \.LC\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "ldr\td\[0-9\]+, \\\[x\[0-9\], #:lo12:\.LC\[0-9\]\\\]" 2 } } */ + +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, 1\\\.5e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c new file mode 100644 index 00000000000..1ed3831e139 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +extern __fp16 foo (); +extern void bar (__fp16* x); + +void f1 () +{ + volatile __fp16 a = 17.0; +} + + +void f2 (__fp16 *a) +{ + *a = 17.0; +} + +void f3 () +{ + __fp16 b = foo (); + b = 17.0; + bar (&b); +} + +__fp16 f4 () +{ + __fp16 a = 0; + __fp16 b = 1; + __fp16 c = 2; + __fp16 d = 4; + + __fp16 z = a + b; + z = z + c; + z = z - d; + return z; +} + +__fp16 f5 () +{ + __fp16 a = 16; + bar (&a); + return a; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, #?19520" 3 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0xbc, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x4c, lsl 8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c new file mode 100644 index 00000000000..6f44821e9d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include <arm_fp16.h> + +float16_t f0(void) +{ + float16_t x = 0.0f; + return x; +} + +float16_t fn1(void) +{ + float16_t x = -0.0f; + return x; +} + +float16_t f1(void) +{ + float16_t x = 256.0f; + return x; +} + +float16_t f2(void) +{ + float16_t x = 123256.0f; + return x; +} + +float16_t f3(void) +{ + float16_t x = 17.0; + return x; +} + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.4h, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x5c, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x7c, lsl 8" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 19520" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\th\[0-9\], w\[0-9\]+" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c new file mode 100644 index 00000000000..7b92a5ae40f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +float f0(void) +{ + float x = 0.0f; + return x; +} + +float fn1(void) +{ + float x = -0.0f; + return x; +} + +float f1(void) +{ + float x = 256.0f; + return x; +} + +float f2(void) +{ + float x = 123256.0f; + return x; +} + +float f3(void) +{ + float x = 2.0f; + return x; +} + +float f4(void) +{ + float x = -20000.1; + return x; +} + + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 48128" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0x47f0, lsl 16" 1 } } */ + +/* { dg-final { scan-assembler-times "fmov\ts\[0-9\]+, 2\\\.0e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 16435" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0xc69c, lsl 16" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c new file mode 100644 index 00000000000..6ac9065037f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3" } */ + +long long f1(void) +{ + return 0xffff6666; +} + +int f3(void) +{ + return 0xffff6666; +} + + +long f2(void) +{ + return 0x11110000ffff6666; +} + +long f4(void) +{ + return 0x11110001ffff6666; +} + +long f5(void) +{ + return 0x111100001ff6666; +} + +long f6(void) +{ + return 0x00001111ffff6666; +} + +long f7(void) +{ + return 0x000011116666ffff; +} + +long f8(void) +{ + return 0x0f0011116666ffff; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 4294927974" 3 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 1718026239" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -2576941057" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 26214" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0xf00, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 48" 2 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1000, lsl 32" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 32" 3 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x111, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1ff, lsl 16" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1, lsl 32" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c index c917f81c022..114d8c1a6c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c +++ b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c @@ -4,10 +4,10 @@ #pragma GCC target ("+nothing+simd, cmodel=small") int -cal (float a) +cal (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -19,11 +19,11 @@ cal (float a) #pragma GCC target ("cmodel=large") int -cal2 (float a) +cal2 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -33,11 +33,11 @@ cal2 (float a) #pragma GCC pop_options int -cal3 (float a) +cal3 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else diff --git a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c new file mode 100644 index 00000000000..a889dfdd895 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ +/* { dg-require-effective-target lp64 } */ + +__int128 +t (void) +{ + return (__int128)1 << 80; +} + +/* { dg-final { scan-assembler "adr" } } */ +/* { dg-final { scan-assembler-not "adrp" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr81414.C b/gcc/testsuite/gcc.target/aarch64/pr81414.C new file mode 100644 index 00000000000..53dfc7cf800 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr81414.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57" } */ + +typedef __Float32x2_t float32x2_t; +float32x2_t +foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) { + return __b * __c + __a; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c index 192bad9879b..8fd428115ba 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c @@ -7,12 +7,10 @@ extern void abort (); -#define CHECK(T, N, R, E) \ +#define CHECK(R, E) \ {\ - int i = 0;\ - for (; i < N; i++)\ - if (* (T *) &R[i] != * (T *) &E[i])\ - abort ();\ + if (__builtin_memcmp (&R, &E, sizeof (R)) != 0)\ + abort ();\ } int @@ -26,8 +24,8 @@ main (int argc, char **argv) float32x2_t f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); float32x2_t f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); - CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); - CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + CHECK (f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (f32x2_ret_maxnm, f32x2_exp_maxnm); /* v{min|max}nm_f32 NaN. */ f32x2_input1 = vdup_n_f32 (__builtin_nanf ("")); @@ -37,8 +35,8 @@ main (int argc, char **argv) f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); - CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); - CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + CHECK (f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (f32x2_ret_maxnm, f32x2_exp_maxnm); /* v{min|max}nmq_f32 normal. */ float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0); @@ -48,8 +46,8 @@ main (int argc, char **argv) float32x4_t f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); float32x4_t f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); - CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); - CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + CHECK (f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (f32x4_ret_maxnm, f32x4_exp_maxnm); /* v{min|max}nmq_f32 NaN. */ f32x4_input1 = vdupq_n_f32 (-__builtin_nanf ("")); @@ -59,8 +57,8 @@ main (int argc, char **argv) f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); - CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); - CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + CHECK (f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (f32x4_ret_maxnm, f32x4_exp_maxnm); /* v{min|max}nm_f64 normal. */ float64x1_t f64x1_input1 = vdup_n_f64 (1.23); @@ -69,16 +67,16 @@ main (int argc, char **argv) float64x1_t f64x1_exp_maxnm = vdup_n_f64 (4.56); float64x1_t f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); float64x1_t f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}_f64 normal. */ float64x1_t f64x1_exp_min = vdup_n_f64 (1.23); float64x1_t f64x1_exp_max = vdup_n_f64 (4.56); float64x1_t f64x1_ret_min = vmin_f64 (f64x1_input1, f64x1_input2); float64x1_t f64x1_ret_max = vmax_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_min, f64x1_exp_min); - CHECK (uint64_t, 1, f64x1_ret_max, f64x1_exp_max); + CHECK (f64x1_ret_min, f64x1_exp_min); + CHECK (f64x1_ret_max, f64x1_exp_max); /* v{min|max}nmq_f64 normal. */ float64x2_t f64x2_input1 = vdupq_n_f64 (1.23); @@ -87,8 +85,8 @@ main (int argc, char **argv) float64x2_t f64x2_exp_maxnm = vdupq_n_f64 (4.56); float64x2_t f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); float64x2_t f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); - CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); - CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + CHECK (f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (f64x2_ret_maxnm, f64x2_exp_maxnm); /* v{min|max}nm_f64 NaN. */ f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); @@ -98,8 +96,8 @@ main (int argc, char **argv) f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}_f64 NaN. */ f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); @@ -109,8 +107,8 @@ main (int argc, char **argv) f64x1_ret_minnm = vmin_f64 (f64x1_input1, f64x1_input2); f64x1_ret_maxnm = vmax_f64 (f64x1_input1, f64x1_input2); - CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); - CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + CHECK (f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (f64x1_ret_maxnm, f64x1_exp_maxnm); /* v{min|max}nmq_f64 NaN. */ f64x2_input1 = vdupq_n_f64 (-__builtin_nan ("")); @@ -120,8 +118,8 @@ main (int argc, char **argv) f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); - CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); - CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + CHECK (f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (f64x2_ret_maxnm, f64x2_exp_maxnm); return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c new file mode 100644 index 00000000000..df777581ab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +typedef short int __attribute__ ((vector_size (16))) v8hi; + +v8hi +mla8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + + +v8hi +mls8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef short int __attribute__ ((vector_size (8))) v4hi; + +v4hi +mla4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4hi +mls4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__ ((vector_size (16))) v4si; + +v4si +mla4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4si +mls4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__((vector_size (8))) v2si; + +v2si +mla2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v2si +mls2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} diff --git a/gcc/testsuite/gcc.target/aarch64/stack-checking.c b/gcc/testsuite/gcc.target/aarch64/stack-checking.c index 1d1530df62b..eaa40581c86 100644 --- a/gcc/testsuite/gcc.target/aarch64/stack-checking.c +++ b/gcc/testsuite/gcc.target/aarch64/stack-checking.c @@ -1,4 +1,5 @@ /* { dg-do run { target { *-*-linux* } } } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-fstack-check" } */ int main(void) diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c new file mode 100644 index 00000000000..33a2c0f45af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f (unsigned char *p) +{ + return p[0] == 50 || p[0] == 52; +} + +int +g (unsigned char *p) +{ + return (p[0] >> 4 & 0xfd) == 0; +} + +/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c new file mode 100644 index 00000000000..0bd326a879d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* The integer variable shift and rotate instructions truncate their + shift amounts by the datasize. Make sure that we don't emit a redundant + masking operation. */ + +unsigned +f1 (unsigned x, int y) +{ + return x << (y & 31); +} + +unsigned long long +f2 (unsigned long long x, int y) +{ + return x << (y & 63); +} + +unsigned long long +f3 (unsigned long long bit_addr, int y) +{ + unsigned long bitnumb = bit_addr & 63; + return (1LL << bitnumb); +} + +unsigned int +f4 (unsigned int x, unsigned int y) +{ + y &= 31; + return x >> y | (x << (32 - y)); +} + +unsigned long long +f5 (unsigned long long x, unsigned long long y) +{ + y &= 63; + return x >> y | (x << (64 - y)); +} + +unsigned int +f6 (unsigned int x, unsigned int y) +{ + return (x << (32 - (y & 31))); +} + +unsigned long long +f7 (unsigned long long x, unsigned long long y) +{ + return (x << (64 - (y & 63))); +} + +unsigned long long +f8 (unsigned long long x, unsigned long long y) +{ + return (x << -(y & 63)); +} + +/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */ +/* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-not "and\tw\[0-9\]+, w\[0-9\]+, 31" } } */ +/* { dg-final { scan-assembler-not "and\tx\[0-9\]+, x\[0-9\]+, 63" } } */ +/* { dg-final { scan-assembler-not "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c index 57cb95b91fc..5fd6c360363 100644 --- a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c +++ b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c @@ -7,7 +7,7 @@ static int id (int i) { - asm ("": "+Xr" (i)); + asm ("": "+r" (i)); return i; } diff --git a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c index 287d96d4ee9..6ec4bc5d875 100644 --- a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c +++ b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c @@ -9,7 +9,7 @@ static int id (int i) { - asm ("": "+Xr" (i)); + asm ("": "+r" (i)); return i; } diff --git a/gcc/testsuite/gcc.target/arc/naked-1.c b/gcc/testsuite/gcc.target/arc/naked-1.c new file mode 100644 index 00000000000..e45f433f73c --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/naked-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ +/* Check that naked functions don't place arguments on the stack at + optimisation level '-O0'. */ +extern void bar (int); + +void __attribute__((naked)) +foo (int n, int m) +{ + bar (n + m); +} +/* { dg-final { scan-assembler "\tbl @bar" } } */ + +/* Look for things that would appear in a non-naked function, but which + should not appear in a naked function. */ +/* { dg-final { scan-assembler-not "\tj.* \\\[blink\\\]" } } */ +/* { dg-final { scan-assembler-not "\tst.* " } } */ +/* { dg-final { scan-assembler-not "\tmov fp,sp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/naked-2.c b/gcc/testsuite/gcc.target/arc/naked-2.c new file mode 100644 index 00000000000..7b7262f7916 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/naked-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ +/* Check that naked functions don't place arguments on the stack at + optimisation level '-O0'. */ + +#if defined(__HS__) || defined(__EM__) +# define ILINK "ilink" +#else +# define ILINK "ilink1" +#endif + +extern void bar (int); + +void __attribute__((naked, interrupt(ILINK))) +foo (int n, int m) +{ + bar (n + m); +} +/* { dg-final { scan-assembler "\tbl @bar" } } */ + +/* Look for things that would appear in a non-naked function, but which + should not appear in a naked function. */ +/* { dg-final { scan-assembler-not "\trtie" } } */ +/* { dg-final { scan-assembler-not "j.*\[ilink1\]" } } */ +/* { dg-final { scan-assembler-not "\tst.* " } } */ +/* { dg-final { scan-assembler-not "\tmov fp,sp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/pic-1.c b/gcc/testsuite/gcc.target/arc/pic-1.c new file mode 100644 index 00000000000..ab24763b67f --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pic-1.c @@ -0,0 +1,11 @@ +/* Tests how complex pic constant expressions are handled. */ +/* { dg-do assemble } */ +/* { dg-skip-if "PIC not available for ARC6xx" { arc6xx } } */ +/* { dg-options "-mno-sdata -w -Os -fpic" } */ + +a() { + char *b = ""; + char c; + int d = &c - " \n\t\v\b\r\f\a/\0"; + e(b[d]); +} diff --git a/gcc/testsuite/gcc.target/arc/pr9000674901.c b/gcc/testsuite/gcc.target/arc/pr9000674901.c new file mode 100644 index 00000000000..2a15c1c1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pr9000674901.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=arc700 -O2 -fpic" } */ + +/* Test if the compiler generates a constant address having that uses + a neg keyword on the pic unspec. */ + +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned long long int uint64_t; + +enum type { + t_undef = 0x01, + t_group = 0x02, + t_partition = 0x04, + t_spare = 0x08, + t_linear = 0x10, + t_raid0 = 0x20, + t_raid1 = 0x40, + t_raid4 = 0x80, + t_raid5_ls = 0x100, + t_raid5_rs = 0x200, + t_raid5_la = 0x400, + t_raid5_ra = 0x800, + t_raid6 = 0x1000, +}; + +struct raid_set { + enum type type; +}; + +void +_find_factors (struct raid_set *rs, uint8_t * div, uint8_t * sub) +{ + struct factors { + const uint8_t level; + const uint8_t div, sub; + }; + static struct factors factors[] = { + {0, 1, 0}, + {1, 2, 0}, + {2, 2, 0}, + {5, 1, 1}, + }; + struct factors *f = (factors + (sizeof (factors) / sizeof (*factors))); + + while (f-- > factors) { + if (rs->type == f->level) { + *div = f->div; + *sub = f->sub; + return; + } + } + + *div = 1; + *sub = 0; +} diff --git a/gcc/testsuite/gcc.target/arc/pr9001191897.c b/gcc/testsuite/gcc.target/arc/pr9001191897.c new file mode 100644 index 00000000000..fc3642629d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pr9001191897.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=archs -Os -fpic -mno-sdata -mno-indexed-loads -w" } */ +a; +c() { + static char b[25]; + for (; a >= 0; a--) + if (b[a]) + b[a] = '\0'; +} diff --git a/gcc/testsuite/gcc.target/arm/lto/pr65837-attr_0.c b/gcc/testsuite/gcc.target/arm/lto/pr65837-attr_0.c index ebc5f447a08..f00480b5c02 100644 --- a/gcc/testsuite/gcc.target/arm/lto/pr65837-attr_0.c +++ b/gcc/testsuite/gcc.target/arm/lto/pr65837-attr_0.c @@ -1,6 +1,7 @@ /* { dg-lto-do run } */ /* { dg-require-effective-target arm_neon_hw } */ -/* { dg-lto-options {{-flto}} } */ +/* { dg-require-effective-target arm_neon_ok_no_float_abi } */ +/* { dg-lto-options {{-flto -mfpu=neon}} } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/lto/pr65837_0.c b/gcc/testsuite/gcc.target/arm/lto/pr65837_0.c index 6b2def9985d..5d7cea7b2e4 100644 --- a/gcc/testsuite/gcc.target/arm/lto/pr65837_0.c +++ b/gcc/testsuite/gcc.target/arm/lto/pr65837_0.c @@ -1,7 +1,7 @@ /* { dg-lto-do run } */ /* { dg-require-effective-target arm_neon_hw } */ +/* { dg-require-effective-target arm_neon_ok_no_float_abi } */ /* { dg-lto-options {{-flto -mfpu=neon}} } */ -/* { dg-suppress-ld-options {-mfpu=neon} } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/stack-checking.c b/gcc/testsuite/gcc.target/arm/stack-checking.c index 88a7e6e8286..4b53bedd97b 100644 --- a/gcc/testsuite/gcc.target/arm/stack-checking.c +++ b/gcc/testsuite/gcc.target/arm/stack-checking.c @@ -1,6 +1,6 @@ /* { dg-do run { target { *-*-linux* } } } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-fstack-check" } */ -/* { dg-skip-if "" { arm_thumb1 } } */ int main(void) { diff --git a/gcc/testsuite/gcc.target/avr/isr-test.h b/gcc/testsuite/gcc.target/avr/isr-test.h new file mode 100644 index 00000000000..176dbc2a15f --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/isr-test.h @@ -0,0 +1,283 @@ +#ifndef ISR_TEST_H +#define ISR_TEST_H + +#include <string.h> + +#define ISR(N,...) \ +__attribute__ ((used, externally_visible , ## __VA_ARGS__)) \ + void __vector_##N (void); \ + void __vector_##N (void) + +#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR))) +#define CORE_SFRS SFR (0x38) +#define SREG SFR (0x3F) +#define SPL SFR (0x3D) +#define EIND SFR (0x3C) +#define RAMPZ SFR (0x3B) +#define RAMPY SFR (0x3A) +#define RAMPX SFR (0x39) +#define RAMPD SFR (0x38) + +#ifdef __AVR_HAVE_JMP_CALL__ +#define VEC_SIZE 4 +#else +#define VEC_SIZE 2 +#endif + +#ifdef __AVR_TINY__ +#define FIRST_REG 16 +#else +#define FIRST_REG 0 +#endif + +#define CR "\n\t" + +typedef struct +{ + unsigned char sfrs[8]; + unsigned char gprs[32 - FIRST_REG]; +} regs_t; + +regs_t reginfo1, reginfo2; + +__attribute__((noinline,unused)) +static void clear_reginfo (void) +{ + memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs)); + memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs)); +} + +__attribute__((noinline,unused)) +static void compare_reginfo (unsigned long gpr_ignore) +{ + signed char regno; + const unsigned char *preg1 = ®info1.gprs[0]; + const unsigned char *preg2 = ®info2.gprs[0]; + + if (memcmp (®info1, ®info2, 8)) + __builtin_abort(); + + gpr_ignore >>= FIRST_REG; + + for (regno = FIRST_REG; regno < 32; + regno++, preg1++, preg2++, gpr_ignore >>= 1) + { + if (gpr_ignore & 1) + continue; + + if (*preg1 != *preg2) + { + static signed char volatile failed_regno; + (void) failed_regno; + failed_regno = regno; + __builtin_abort(); + } + } +} + +/* STore GPR */ +#define ST(regno,M) \ + CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno + +/* STore SFR */ +#define ST_SFR(sfr, n_sfr, M) \ + CR "in __tmp_reg__,%i[s_" #sfr "]" \ + CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__" + +/* Named asm OPerand for SFR */ +#define OP_SFR(sfr) \ + , [s_ ## sfr] "n" (&(sfr)) + +/* Write funny value to SFR */ +#define XX_SFR(sfr) \ + CR "dec r31 $ out %i[s_" #sfr "], r31" + +/* Write 0 to SFR */ +#define OO_SFR(sfr) \ + CR "out %i[s_" #sfr "], __zero_reg__" + +/* Macros for SREG */ +#define ST_SREG(M) ST_SFR (SREG,0,M) +#define OP_SREG OP_SFR (SREG) +#define XX_SREG XX_SFR (SREG) + +/* Macros for EIND */ +#if defined __AVR_HAVE_EIJMP_EICALL__ +#define ST_EIND(M) ST_SFR (EIND,1,M) +#define OP_EIND OP_SFR (EIND) +#else +#define ST_EIND(M) /* empty */ +#define OP_EIND /* empty */ +#endif + +/* Macros for RAMPX */ +#if defined (__AVR_HAVE_RAMPX__) +#define ST_RAMPX(M) ST_SFR (RAMPX,2,M) +#define OP_RAMPX OP_SFR (RAMPX) +#define XX_RAMPX XX_SFR (RAMPX) +#define OO_RAMPX OO_SFR (RAMPX) +#else +#define ST_RAMPX(M) /* empty */ +#define OP_RAMPX /* empty */ +#define XX_RAMPX /* empty */ +#define OO_RAMPX /* empty */ +#endif + +/* Macros for RAMPY */ +#if defined (__AVR_HAVE_RAMPY__) +#define ST_RAMPY(M) ST_SFR (RAMPY,3,M) +#define OP_RAMPY OP_SFR (RAMPY) +#define XX_RAMPY XX_SFR (RAMPY) +#define OO_RAMPY OO_SFR (RAMPY) +#else +#define ST_RAMPY(M) /* empty */ +#define OP_RAMPY /* empty */ +#define XX_RAMPY /* empty */ +#define OO_RAMPY /* empty */ +#endif + +/* Macros for RAMPZ */ +#if defined (__AVR_HAVE_RAMPZ__) +#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M) +#define OP_RAMPZ OP_SFR (RAMPZ) +#define XX_RAMPZ XX_SFR (RAMPZ) +#define OO_RAMPZ OO_SFR (RAMPZ) +#else +#define ST_RAMPZ(M) /* empty */ +#define OP_RAMPZ /* empty */ +#define XX_RAMPZ /* empty */ +#define OO_RAMPZ /* empty */ +#endif + +/* Macros for RAMPD */ +#if defined (__AVR_HAVE_RAMPD__) +#define ST_RAMPD(M) ST_SFR (RAMPD,5,M) +#define OP_RAMPD OP_SFR (RAMPD) +#else +#define ST_RAMPD(M) /* empty */ +#define OP_RAMPD /* empty */ +#endif + +/* Macros for all GPRs */ +#if defined __AVR_TINY__ +#define ST_REGS_LO(M) /* empty */ +#else +#define ST_REGS_LO(M) \ + ST(0,M) ST(1,M) ST(2,M) ST(3,M) \ + ST(4,M) ST(5,M) ST(6,M) ST(7,M) \ + ST(8,M) ST(9,M) ST(10,M) ST(11,M) \ + ST(12,M) ST(13,M) ST(14,M) ST(15,M) +#endif /* AVR_TINY */ + +#define ST_REGS_HI(M) \ + ST(16,M) ST(17,M) ST(18,M) ST(19,M) \ + ST(20,M) ST(21,M) ST(22,M) ST(23,M) \ + ST(24,M) ST(25,M) ST(26,M) ST(27,M) \ + ST(28,M) ST(29,M) ST(30,M) ST(31,M) + +__attribute__((unused,naked,noinline,noclone)) +static void host_store1 (void) +{ + __asm __volatile__ + ("nop" + CR ".global do_stores_before" + CR ".type do_stores_before,@function" + CR "do_stores_before:" + /* Funny values to some SFRs */ + CR "ldi r31, 1 + 'Z'" + XX_RAMPZ + XX_RAMPY + XX_RAMPX + CR "dec __zero_reg__" + CR "clr r31" + XX_SREG + /* Must set I-flag due to RETI of ISR */ + CR "sei" + /* Store core regs before ISR */ + ST_RAMPX (mem1) + ST_RAMPY (mem1) + ST_RAMPZ (mem1) + ST_RAMPD (mem1) + ST_EIND (mem1) + ST_SREG (mem1) + CR "ldi r31, 0xaa" + CR "mov __tmp_reg__, r31" + CR "ldi r31, 31" + ST_REGS_LO (mem1) + ST_REGS_HI (mem1) + CR "ret" + : /* No outputs */ + : [mem1] "i" (®info1), [first] "n" (FIRST_REG) + OP_RAMPX + OP_RAMPY + OP_RAMPZ + OP_RAMPD + OP_EIND + OP_SREG + : "memory", "r31"); +} + +__attribute__((unused,naked,noinline,noclone)) +static void host_store2 (void) +{ + __asm __volatile__ + ("nop" + CR ".global do_stores_after" + CR ".type do_stores_after,@function" + CR "do_stores_after:" + /* Store core regs after ISR */ + ST_REGS_LO (mem2) + ST_REGS_HI (mem2) + ST_RAMPX (mem2) + ST_RAMPY (mem2) + ST_RAMPZ (mem2) + ST_RAMPD (mem2) + ST_EIND (mem2) + ST_SREG (mem2) + /* Undo funny values */ + CR "clr __zero_reg__" + OO_RAMPX + OO_RAMPY + OO_RAMPZ + CR "ret" + : /* No outputs */ + : [mem2] "i" (®info2), [first] "n" (FIRST_REG) + OP_RAMPX + OP_RAMPY + OP_RAMPZ + OP_RAMPD + OP_EIND + OP_SREG + : "memory"); +} + +#define MK_CALL_ISR(vecno) \ + __asm __volatile__ \ + (/* Funny values to some SFRs */ \ + /* Must set I-flag due to RETI of ISR */ \ + /* Store core regs before ISR */ \ + CR "%~call do_stores_before" \ + /* Execute ISR */ \ + CR "%~call __vectors + %[vect]" \ + /* Store core regs after ISR */ \ + /* Undo funny values */ \ + CR "%~call do_stores_after" \ + : /* No outputs */ \ + : [vect] "i" (VEC_SIZE * (vecno)) \ + , "i" (host_store1) \ + , "i" (host_store2) \ + : "memory", "r31") + + +#define MK_RUN_ISR(N, IGMSK) \ + \ +__attribute__((noinline,noclone)) \ +void run_isr_ ## N (void) \ +{ \ + clear_reginfo(); \ + MK_CALL_ISR (N); \ + compare_reginfo (IGMSK); \ +} + +#endif /* ISR_TEST_H */ + diff --git a/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c b/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c new file mode 100644 index 00000000000..271d0cf47e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-options "-std=c99" } */ + +#include "../isr-test.h" + +int volatile v; + +/**********************************************************************/ + +ISR (1, signal) +{ +} + +MK_RUN_ISR (1, 0) + +void test1 (void) +{ + run_isr_1(); +} + +/**********************************************************************/ + +ISR (2, signal) +{ + v++; +} + +MK_RUN_ISR (2, 0) + +void test2 (void) +{ + v = 0; + run_isr_2(); + if (v != 1) + __builtin_abort(); +} + + +/**********************************************************************/ + +ISR (3, signal) +{ + __asm __volatile__ ("$ lds r27, v" + "$ swap r27" + "$ sts v, r27" + ::: "memory", "r27"); +} + +MK_RUN_ISR (3, 0) + +void test3 (void) +{ + run_isr_3(); + if (v != 0x10) + __builtin_abort(); +} + +/**********************************************************************/ + +ISR (4, signal) +{ + __asm __volatile__ ("sts v,__zero_reg__" ::: "memory"); +} + +MK_RUN_ISR (4, 0) + +void test4 (void) +{ + run_isr_4(); + if (v != 0) + __builtin_abort(); +} + +/**********************************************************************/ + +ISR (5, signal) +{ + __asm __volatile__ ("clt"); +} + +MK_RUN_ISR (5, 0) + +void test5 (void) +{ + run_isr_5(); +} + +/**********************************************************************/ + +int main (void) +{ + test1(); + test2(); + test3(); + test4(); + test5(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c b/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c new file mode 100644 index 00000000000..be4f22ebb35 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-std=c99" } */ + +#include "../isr-test.h" + +int volatile v; + +__attribute__((noinline,noclone)) +void inc_v (void) +{ + v++; +} + +/**********************************************************************/ + +ISR (1, signal) +{ + inc_v(); +} + +MK_RUN_ISR (1, 0) + +void test1 (void) +{ + run_isr_1(); + if (v != 1) + __builtin_abort(); +} + +/**********************************************************************/ + +ISR (2, signal) +{ + if (v == 1) + inc_v(); + else + v += 2; +} + +MK_RUN_ISR (2, 0) + +void test2 (void) +{ + run_isr_2(); + if (v != 2) + __builtin_abort(); + run_isr_2(); + if (v != 4) + __builtin_abort(); +} + + +/**********************************************************************/ + +int main (void) +{ + test1(); + test2(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c b/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c new file mode 100644 index 00000000000..5606225aebc --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c @@ -0,0 +1,146 @@ +/* { dg-do run } */ +/* { dg-options "-std=gnu99 -fno-lto -fno-toplevel-reorder" } */ + +// No LTO for now due to PR lto/68384. + +#ifdef __AVR_TINY__ +unsigned char reg2; +#else +register unsigned char reg2 __asm("r2"); +#endif + +#include "../isr-test.h" + +#define SET_REG(reg,val) \ + do { \ + reg = (val); \ + __asm __volatile__("" : "+r" (reg)); \ + } while (0) \ + +#define GET_REG(reg) \ + ({ \ + __asm __volatile__("" : "+r" (reg)); \ + reg; \ + }) + +/**********************************************************************/ + +ISR (1, signal) +{ + reg2++; +} + +MK_RUN_ISR (1, 1ul << 2) + +void test1 (void) +{ + SET_REG (reg2, 0); + run_isr_1(); + if (GET_REG (reg2) != 1) + __builtin_abort(); +} + +/**********************************************************************/ + +__attribute__((noinline,noclone)) +void inc_r2 (void) +{ + reg2++; +} + +ISR (2, signal) +{ + inc_r2 (); +} + +MK_RUN_ISR (2, 1ul << 2) + +void test2 (void) +{ + run_isr_2(); + if (GET_REG (reg2) != 2) + __builtin_abort(); +} + + +/**********************************************************************/ + +ISR (3, signal) +{ +#ifndef __AVR_TINY__ + register char r4 __asm ("r4"); + __asm __volatile ("inc %0" : "+r" (r4)); + __asm __volatile ("inc r5" ::: "r5"); +#endif +} + +MK_RUN_ISR (3, 0) + +void test3 (void) +{ + run_isr_3(); +} + + +/**********************************************************************/ + +#define CLOBB(reg) \ + do { \ + __asm __volatile__ ("inc " #reg ::: #reg); \ + } while (0) + +ISR (4, signal) +{ + char volatile v; + v = 1; + +#ifndef __AVR_TINY__ + CLOBB (r3); + CLOBB (r4); + CLOBB (r5); + CLOBB (r6); + CLOBB (r7); + CLOBB (r8); + CLOBB (r9); + CLOBB (r10); + CLOBB (r11); + CLOBB (r12); + CLOBB (r13); + CLOBB (r14); + CLOBB (r15); + CLOBB (r16); + CLOBB (r17); +#endif + + CLOBB (r18); + CLOBB (r19); + CLOBB (r20); + CLOBB (r21); + CLOBB (r22); + CLOBB (r23); + CLOBB (r24); + CLOBB (r25); + CLOBB (r26); + CLOBB (r27); + CLOBB (r30); + CLOBB (r31); +} + +MK_RUN_ISR (4, 0) + +void test4 (void) +{ + run_isr_4(); +} + + +/**********************************************************************/ + +int main (void) +{ + test1(); + test2(); + test3(); + test4(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c index b1da555bc31..ddee754c962 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c @@ -44,9 +44,9 @@ adx_test (void) sum_ref = 0x0; /* X = 0x00000001, Y = 0x00000000, C = 0. */ - c = _subborrow_u32 (c, x, y, &x); + c = _subborrow_u32 (c, y, x, &x); /* X = 0xFFFFFFFF, Y = 0x00000000, C = 1. */ - c = _subborrow_u32 (c, x, y, &x); + c = _subborrow_u32 (c, y, x, &x); /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 1. */ if (x != sum_ref) diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c index b326291bb35..287e263a9dd 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c @@ -44,9 +44,9 @@ adx_test (void) sum_ref = 0x0LL; /* X = 0x0000000000000001, Y = 0x0000000000000000, C = 0. */ - c = _subborrow_u64 (c, x, y, &x); + c = _subborrow_u64 (c, y, x, &x); /* X = 0xFFFFFFFFFFFFFFFF, Y = 0x0000000000000000, C = 1. */ - c = _subborrow_u64 (c, x, y, &x); + c = _subborrow_u64 (c, y, x, &x); /* X = 0x0000000000000000, Y = 0x0000000000000000, C = 1. */ if (x != sum_ref) diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 8377555f815..085ba81a672 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -233,11 +233,15 @@ #define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8) #define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8) #define __builtin_ia32_getexpsd128_round(A, B, C) __builtin_ia32_getexpsd128_round(A, B, 4) +#define __builtin_ia32_getexpsd_mask_round(A, B, C, D, E) __builtin_ia32_getexpsd_mask_round(A, B, C, D, 4) #define __builtin_ia32_getexpss128_round(A, B, C) __builtin_ia32_getexpss128_round(A, B, 4) +#define __builtin_ia32_getexpss_mask_round(A, B, C, D, E) __builtin_ia32_getexpss_mask_round(A, B, C, D, 4) #define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantsd_round(A, B, C, D) __builtin_ia32_getmantsd_round(A, B, 1, 4) +#define __builtin_ia32_getmantsd_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsd_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_getmantss_round(A, B, C, D) __builtin_ia32_getmantss_round(A, B, 1, 4) +#define __builtin_ia32_getmantss_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantss_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E) #define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E) diff --git a/gcc/testsuite/gcc.target/i386/avx-pr80846.c b/gcc/testsuite/gcc.target/i386/avx-pr80846.c new file mode 100644 index 00000000000..338f01039f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr80846.c @@ -0,0 +1,39 @@ +/* PR target/80846 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx -mno-avx2" } */ + +typedef __int128 V __attribute__((vector_size (32))); +typedef long long W __attribute__((vector_size (32))); +typedef int X __attribute__((vector_size (16))); +typedef __int128 Y __attribute__((vector_size (64))); +typedef long long Z __attribute__((vector_size (64))); + +W f1 (__int128 x, __int128 y) { return (W) ((V) { x, y }); } +__int128 f2 (W x) { return ((V)x)[0]; } +__int128 f3 (W x) { return ((V)x)[1]; } +W f4 (X x, X y) { union { X x; __int128 i; } u = { .x = x }, v = { .x = y }; return (W) ((V) { u.i, v.i }); } +X f5 (W x) { return (X)(((V)x)[0]); } +X f6 (W x) { return (X)(((V)x)[1]); } +W f7 (void) { return (W) ((V) { 2, 3 }); } +W f8 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { u.i, 3 }); } +W f9 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { 2, u.i }); } +W f10 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { u.i, u.i }); } +#ifdef __AVX512F__ +Z f11 (__int128 x, __int128 y, __int128 z, __int128 a) { return (Z) ((Y) { x, y, z, a }); } +__int128 f12 (Z x) { return ((Y)x)[0]; } +__int128 f13 (Z x) { return ((Y)x)[1]; } +__int128 f14 (Z x) { return ((Y)x)[2]; } +__int128 f15 (Z x) { return ((Y)x)[3]; } +Z f16 (X x, X y, X z, X a) { union { X x; __int128 i; } u = { .x = x }, v = { .x = y }, w = { .x = z }, t = { .x = a }; + return (Z) ((Y) { u.i, v.i, w.i, t.i }); } +X f17 (Z x) { return (X)(((Y)x)[0]); } +X f18 (Z x) { return (X)(((Y)x)[1]); } +X f19 (Z x) { return (X)(((Y)x)[2]); } +X f20 (Z x) { return (X)(((Y)x)[3]); } +Z f21 (void) { return (Z) ((Y) { 2, 3, 4, 5 }); } +Z f22 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { u.i, 3, 4, 5 }); } +Z f23 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, u.i, 4, 5 }); } +Z f24 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, 3, u.i, 5 }); } +Z f25 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, 3, 4, u.i }); } +Z f26 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { u.i, u.i, u.i, u.i }); } +#endif diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr80846.c b/gcc/testsuite/gcc.target/i386/avx2-pr80846.c new file mode 100644 index 00000000000..907fd4f7b62 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-pr80846.c @@ -0,0 +1,5 @@ +/* PR target/80846 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx2 -mno-avx512f" } */ + +#include "avx-pr80846.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c new file mode 100644 index 00000000000..6ebaed6f715 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c @@ -0,0 +1,5 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mno-avx512dq" } */ + +#include "avx512dq-pr81532.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c new file mode 100644 index 00000000000..39632a2c482 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c @@ -0,0 +1,12 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw" } */ + +typedef unsigned __int128 V __attribute__ ((vector_size (64))); + +V +foo (V c) +{ + c >>= 0 != c; + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr80846.c b/gcc/testsuite/gcc.target/i386/avx512f-pr80846.c new file mode 100644 index 00000000000..c32c9762cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr80846.c @@ -0,0 +1,5 @@ +/* PR target/80846 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512f" } */ + +#include "avx-pr80846.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-3.c new file mode 100644 index 00000000000..fbe09b1220b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_add (double *r, double *s1, double *s2) +{ + r[0] = s1[0] + s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_add_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_add_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_add_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_add_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_add (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_add (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vaddss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vaddss-3.c new file mode 100644 index 00000000000..45fb29594e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vaddss-3.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_add (float *r, float *s1, float *s2) +{ + r[0] = s1[0] + s2[0]; + + int i; + for (i = 1; i < SIZE; i++) + r[i] = s1[i]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_add_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_add_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_add_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_add_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_add (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_add (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-3.c new file mode 100644 index 00000000000..0baaf75e194 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_div (double *r, double *s1, double *s2) +{ + r[0] = s1[0] / s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_div_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_div_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_div_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_div_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_div (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_div (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vdivss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vdivss-3.c new file mode 100644 index 00000000000..d337bb21182 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vdivss-3.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_div (float *r, float *s1, float *s2) +{ + r[0] = s1[0] / s2[0]; + int i; + for (i = 1; i < SIZE; i++) + r[i] = s1[i]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_div_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_div_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_div_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_div_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_div (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_div (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c index 63194a38b17..226cd9665ca 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c @@ -1,15 +1,24 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -O2" } */ /* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> volatile __m128d x; +volatile __mmask8 m; void extern avx512f_test (void) { x = _mm_getexp_sd (x, x); + x = _mm_mask_getexp_sd (x, m, x, x); + x = _mm_maskz_getexp_sd (m, x, x); x = _mm_getexp_round_sd (x, x, _MM_FROUND_NO_EXC); + x = _mm_mask_getexp_round_sd (x, m, x, x, _MM_FROUND_NO_EXC); + x = _mm_maskz_getexp_round_sd (m, x, x, _MM_FROUND_NO_EXC); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c index 4f7c94db9ae..cb82448725f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c @@ -6,30 +6,61 @@ #include <math.h> #include "avx512f-check.h" +#include "avx512f-helper.h" +#include "avx512f-mask-type.h" static void compute_vgetexpsd (double *s, double *r) { r[0] = floor (log (s[0]) / log (2)); + r[1] = s[1]; } void static avx512f_test (void) { int i; - union128d res1, s1; + union128d res1, res2, res3, res4, res5, res6, s1; + MASK_TYPE mask = MASK_VALUE; double res_ref[SIZE]; for (i = 0; i < SIZE; i++) { s1.a[i] = 5.0 - i; - res_ref[i] = s1.a[i]; + res2.a[i] = DEFAULT_VALUE; + res5.a[i] = DEFAULT_VALUE; } res1.x = _mm_getexp_sd (s1.x, s1.x); + res2.x = _mm_mask_getexp_sd (res2.x, mask, s1.x, s1.x); + res3.x = _mm_maskz_getexp_sd (mask, s1.x, s1.x); + res4.x = _mm_getexp_round_sd (s1.x, s1.x, _MM_FROUND_NO_EXC); + res5.x = _mm_mask_getexp_round_sd (res5.x, mask, s1.x, s1.x, _MM_FROUND_NO_EXC); + res6.x = _mm_maskz_getexp_round_sd (mask, s1.x, s1.x, _MM_FROUND_NO_EXC); compute_vgetexpsd (s1.a, res_ref); if (check_fp_union128d (res1, res_ref)) abort (); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_fp_union128d (res2, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_fp_union128d (res3, res_ref)) + abort (); + + compute_vgetexpsd (s1.a, res_ref); + + if (check_fp_union128d (res4, res_ref)) + abort (); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_fp_union128d (res5, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_fp_union128d (res6, res_ref)) + abort (); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c index 9103e6ad84f..495b93c9c6a 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c @@ -1,15 +1,24 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -O2" } */ /* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> volatile __m128 x; +volatile __mmask8 m; void extern avx512f_test (void) { x = _mm_getexp_ss (x, x); + x = _mm_mask_getexp_ss (x, m, x, x); + x = _mm_maskz_getexp_ss (m, x, x); x = _mm_getexp_round_ss (x, x, _MM_FROUND_NO_EXC); + x = _mm_mask_getexp_round_ss (x, m, x, x, _MM_FROUND_NO_EXC); + x = _mm_maskz_getexp_round_ss (m, x, x, _MM_FROUND_NO_EXC); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c index 926f4d87ffb..ed193af78d4 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c @@ -6,30 +6,63 @@ #include <math.h> #include "avx512f-check.h" +#include "avx512f-helper.h" +#include "avx512f-mask-type.h" static void compute_vgetexpss (float *s, float *r) { + int i; r[0] = floor (log (s[0]) / log (2)); + for(i = 1; i < SIZE; i++) + r[i] = s[i]; } void static avx512f_test (void) { int i; - union128 res1, s1; + union128 res1, res2, res3, res4, res5, res6, s1; + MASK_TYPE mask = MASK_VALUE; float res_ref[SIZE]; for (i = 0; i < SIZE; i++) { s1.a[i] = 5.0 - i; - res_ref[i] = s1.a[i]; + res2.a[i] = DEFAULT_VALUE; + res5.a[i] = DEFAULT_VALUE; } res1.x = _mm_getexp_ss (s1.x, s1.x); + res2.x = _mm_mask_getexp_ss (res2.x, mask, s1.x, s1.x); + res3.x = _mm_maskz_getexp_ss (mask, s1.x, s1.x); + res4.x = _mm_getexp_round_ss (s1.x, s1.x, _MM_FROUND_NO_EXC); + res5.x = _mm_mask_getexp_round_ss (res5.x, mask, s1.x, s1.x, _MM_FROUND_NO_EXC); + res6.x = _mm_maskz_getexp_round_ss (mask, s1.x, s1.x, _MM_FROUND_NO_EXC); compute_vgetexpss (s1.a, res_ref); if (check_fp_union128 (res1, res_ref)) abort (); + + MASK_MERGE () (res_ref, mask, 1); + if (check_fp_union128 (res2, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_fp_union128 (res3, res_ref)) + abort (); + + compute_vgetexpss (s1.a, res_ref); + + if (check_fp_union128 (res4, res_ref)) + abort (); + + MASK_MERGE () (res_ref, mask, 1); + if (check_fp_union128 (res5, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_fp_union128 (res6, res_ref)) + abort (); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c index c501ba6729e..25a64202ea7 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c @@ -1,16 +1,24 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mavx512f" } */ /* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> volatile __m128d x, y, z; +volatile __mmask8 m; void extern avx512f_test (void) { x = _mm_getmant_sd (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); - x = _mm_getmant_round_sd (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, - _MM_FROUND_NO_EXC); + x = _mm_mask_getmant_sd (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_maskz_getmant_sd (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_getmant_round_sd (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src,_MM_FROUND_NO_EXC); + x = _mm_mask_getmant_round_sd (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm_maskz_getmant_round_sd (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c index 3a34ca4f05d..45875b4a921 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c @@ -5,6 +5,10 @@ #include "avx512f-check.h" #include <math.h> +#include "avx512f-helper.h" + +#define SIZE (128/64) +#include "avx512f-mask-type.h" union fp_int_t { @@ -76,18 +80,51 @@ compute_vgetmantsd (double *r, double *s1, double *s2, int interv, static void avx512f_test (void) { - union128d res1, src1, src2; + union128d res1, res2, res3, res4, res5, res6, src1, src2; double res_ref[2]; - int interv = _MM_MANT_NORM_p5_1; - int signctrl = _MM_MANT_SIGN_src; + MASK_TYPE mask = MASK_VALUE; src1.x = _mm_set_pd (-3.0, 111.111); src2.x = _mm_set_pd (222.222, -2.0); + + int i; + for (i = 0; i < SIZE; i++) + { + res2.a[i] = DEFAULT_VALUE; + res5.a[i] = DEFAULT_VALUE; + } - res1.x = _mm_getmant_sd (src1.x, src2.x, interv, signctrl); + res1.x = _mm_getmant_sd (src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res2.x = _mm_mask_getmant_sd (res2.x, mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res3.x = _mm_maskz_getmant_sd (mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res4.x = _mm_getmant_round_sd (src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + res5.x = _mm_mask_getmant_round_sd (res5.x, mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + res6.x = _mm_maskz_getmant_round_sd (mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); - compute_vgetmantsd (res_ref, src1.a, src2.a, interv, signctrl); + compute_vgetmantsd (res_ref, src1.a, src2.a, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); if (check_union128d (res1, res_ref)) abort (); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + compute_vgetmantsd (res_ref, src1.a, src2.a, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + + if (check_union128d (res4, res_ref)) + abort (); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res5, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res6, res_ref)) + abort (); + } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c index 8ce9d467806..00a055ffeee 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c @@ -1,16 +1,24 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mavx512f" } */ /* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include <immintrin.h> volatile __m128 x, y, z; +volatile __mmask8 m; void extern avx512f_test (void) { x = _mm_getmant_ss (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); - x = _mm_getmant_round_ss (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, - _MM_FROUND_NO_EXC); + x = _mm_mask_getmant_ss (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_maskz_getmant_ss (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_getmant_round_ss (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm_mask_getmant_round_ss (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm_maskz_getmant_round_ss (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c index 7c30ea7d8e6..bcd449b4ae2 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c @@ -5,6 +5,10 @@ #include "avx512f-check.h" #include <math.h> +#include "avx512f-helper.h" + +#define SIZE (128/32) +#include "avx512f-mask-type.h" union fp_int_t { @@ -72,7 +76,7 @@ compute_vgetmantss (float *r, float *s1, float *s2, int interv, { int i; r[0] = get_norm_mant (s2[0], signctrl, interv); - for (i = 1; i < 4; i++) + for (i = 1; i < SIZE; i++) { r[i] = s1[i]; } @@ -81,18 +85,50 @@ compute_vgetmantss (float *r, float *s1, float *s2, int interv, static void avx512f_test (void) { - union128 res1, src1, src2; + union128 res1, res2, res3, res4, res5, res6, src1, src2; float res_ref[4]; - int interv = _MM_MANT_NORM_p5_1; - int signctrl = _MM_MANT_SIGN_src; + MASK_TYPE mask = MASK_VALUE; src1.x = _mm_set_ps (-24.043, 68.346, -43.35, 546.46); src2.x = _mm_set_ps (222.222, 333.333, 444.444, -2.0); - res1.x = _mm_getmant_ss (src1.x, src2.x, interv, signctrl); + int i; + for (i = 0; i < SIZE; i++) + { + res2.a[i] = DEFAULT_VALUE; + res5.a[i] = DEFAULT_VALUE; + } + + res1.x = _mm_getmant_ss (src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res2.x = _mm_mask_getmant_ss (res2.x, mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res3.x = _mm_maskz_getmant_ss (mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + res4.x = _mm_getmant_round_ss (src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + res5.x = _mm_mask_getmant_round_ss (res5.x, mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + res6.x = _mm_maskz_getmant_round_ss (mask, src1.x, src2.x, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); - compute_vgetmantss (res_ref, src1.a, src2.a, interv, signctrl); + compute_vgetmantss (res_ref, src1.a, src2.a, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); if (check_union128 (res1, res_ref)) abort (); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + compute_vgetmantss (res_ref, src1.a, src2.a, _MM_MANT_NORM_p5_1, _MM_MANT_SIGN_src); + + if (check_union128 (res4, res_ref)) + abort (); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res5, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res6, res_ref)) + abort (); } diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-3.c new file mode 100644 index 00000000000..95c9c6335af --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_max (double *r, double *s1, double *s2) +{ + r[0] = s1[0] > s2[0] ? s1[0] : s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_max_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_max_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_max_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_max_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_max (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_max (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-3.c new file mode 100644 index 00000000000..e40c891001b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-3.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_max (float *r, float *s1, float *s2) +{ + r[0] = s1[0] > s2[0] ? s1[0] : s2[0]; + int i; + for (i = 1; i < SIZE; i++) + { + r[i] = s1[i]; + } +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_max_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_max_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_max_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_max_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_max (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_max (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vminsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vminsd-3.c new file mode 100644 index 00000000000..eac806b0f23 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vminsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_min (double *r, double *s1, double *s2) +{ + r[0] = s1[0] < s2[0] ? s1[0] : s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_min_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_min_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_min_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_min_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_min (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_min (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vminss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vminss-3.c new file mode 100644 index 00000000000..0ecddd6803e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vminss-3.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_min (float *r, float *s1, float *s2) +{ + r[0] = s1[0] < s2[0] ? s1[0] : s2[0]; + int i; + for (i = 1; i < SIZE; i++) + { + r[i] = s1[i]; + } +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_min_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_min_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_min_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_min_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_min (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_min (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-3.c new file mode 100644 index 00000000000..f6afb693e68 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_mul (double *r, double *s1, double *s2) +{ + r[0] = s1[0] * s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_mul_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_mul_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_mul_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_mul_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_mul (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_mul (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vmulss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vmulss-3.c new file mode 100644 index 00000000000..3d579905bae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vmulss-3.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_mul (float *r, float *s1, float *s2) +{ + r[0] = s1[0] * s2[0]; + int i; + for (i = 1; i < SIZE; i++) + r[i] = s1[i]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_mul_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_mul_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_mul_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_mul_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_mul (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_mul (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c index dbd4544c39e..b36a9c2da0a 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c @@ -41,18 +41,14 @@ TEST (void) res3.a[i] = DEFAULT_VALUE; } -#if AVX512F_LEN == 512 res1.x = INTRINSIC (_permutexvar_epi32) (src1.x, src2.x); -#endif res2.x = INTRINSIC (_maskz_permutexvar_epi32) (mask, src1.x, src2.x); res3.x = INTRINSIC (_mask_permutexvar_epi32) (res3.x, mask, src1.x, src2.x); CALC (src1.a, src2.a, res_ref); -#if AVX512F_LEN == 512 if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref)) abort (); -#endif MASK_ZERO (i_d) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref)) diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c index 770d5623f5f..dd88cd46c0b 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c @@ -40,18 +40,14 @@ TEST (void) res3.a[i] = DEFAULT_VALUE; } -#if AVX512F_LEN == 512 res1.x = INTRINSIC (_permutex_epi64) (src1.x, IMM_MASK); -#endif res2.x = INTRINSIC (_maskz_permutex_epi64) (mask, src1.x, IMM_MASK); res3.x = INTRINSIC (_mask_permutex_epi64) (res3.x, mask, src1.x, IMM_MASK); CALC (src1.a, IMM_MASK, res_ref); -#if AVX512F_LEN == 512 if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref)) abort (); -#endif MASK_ZERO (i_q) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref)) diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c index c596b1d9c40..6c222888e88 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c @@ -41,18 +41,14 @@ TEST (void) res3.a[i] = DEFAULT_VALUE; } -#if AVX512F_LEN == 512 res1.x = INTRINSIC (_permutexvar_epi64) (src1.x, src2.x); -#endif res2.x = INTRINSIC (_maskz_permutexvar_epi64) (mask, src1.x, src2.x); res3.x = INTRINSIC (_mask_permutexvar_epi64) (res3.x, mask, src1.x, src2.x); CALC (src1.a, src2.a, res_ref); -#if AVX512F_LEN == 512 if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref)) abort (); -#endif MASK_ZERO (i_q) (res_ref, mask, SIZE); if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref)) diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-3.c new file mode 100644 index 00000000000..d9f79133937 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-3.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +static void +calc_sub (double *r, double *s1, double *s2) +{ + r[0] = s1[0] - s2[0]; + r[1] = s1[1]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128d res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + double res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_sub_sd (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_sub_sd (mask, src1.x, src2.x); + res3.x = _mm_mask_sub_round_sd (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_sub_round_sd (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_sub (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res1, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res2, res_ref)) + abort (); + + calc_sub (res_ref, src1.a, src2.a); + + MASK_MERGE (d) (res_ref, mask, 1); + if (check_union128d (res3, res_ref)) + abort (); + + MASK_ZERO (d) (res_ref, mask, 1); + if (check_union128d (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vsubss-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vsubss-3.c new file mode 100644 index 00000000000..bd597c959a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vsubss-3.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#include "avx512f-check.h" + +#include "avx512f-helper.h" + +#define SIZE (128 / 32) +#include "avx512f-mask-type.h" + +static void +calc_sub (float *r, float *s1, float *s2) +{ + r[0] = s1[0] - s2[0]; + int i; + for (i = 1; i < SIZE; i++) + r[i] = s1[i]; +} + +void +avx512f_test (void) +{ + int i, sign; + union128 res1, res2, res3, res4, src1, src2; + MASK_TYPE mask = 0; + float res_ref[SIZE]; + + sign = -1; + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1.5 + 34.67 * i * sign; + src2.a[i] = -22.17 * i * sign + 1.0; + res1.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + sign = sign * -1; + } + + res1.x = _mm_mask_sub_ss (res1.x, mask, src1.x, src2.x); + res2.x = _mm_maskz_sub_ss (mask, src1.x, src2.x); + res3.x = _mm_mask_sub_round_ss (res3.x, mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + res4.x = _mm_maskz_sub_round_ss (mask, src1.x, src2.x, _MM_FROUND_NO_EXC); + + calc_sub (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res1, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res2, res_ref)) + abort (); + + calc_sub (res_ref, src1.a, src2.a); + + MASK_MERGE () (res_ref, mask, 1); + if (check_union128 (res3, res_ref)) + abort (); + + MASK_ZERO () (res_ref, mask, 1); + if (check_union128 (res4, res_ref)) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermd-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermd-1.c index fa1aaa390ab..069bb5d6c63 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpermd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermd-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -11,6 +12,7 @@ volatile __mmask8 m; void extern avx512vl_test (void) { + x = _mm256_permutexvar_epi32 (x, x); x = _mm256_maskz_permutexvar_epi32 (m, x, x); x = _mm256_mask_permutexvar_epi32 (x, m, x, x); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-imm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-imm-1.c index c74c8ce96c7..2340a6d9993 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-imm-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-imm-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -11,6 +12,7 @@ volatile __mmask8 m; void extern avx512vl_test (void) { + x = _mm256_permutex_epi64 (x, 13); x = _mm256_mask_permutex_epi64 (x, m, x, 13); x = _mm256_maskz_permutex_epi64 (m, x, 13); } diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-var-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-var-1.c index 43ccad3d6c1..69185e50f76 100644 --- a/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-var-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpermq-var-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ @@ -11,6 +12,7 @@ volatile __mmask8 m; void extern avx512vl_test (void) { + x = _mm256_permutexvar_epi64 (x, x); x = _mm256_maskz_permutexvar_epi64 (m, x, x); x = _mm256_mask_permutexvar_epi64 (x, m, x, x); } diff --git a/gcc/testsuite/gcc.target/i386/cmov7.c b/gcc/testsuite/gcc.target/i386/cmov7.c index 8d637504fd7..e648fed8b2a 100644 --- a/gcc/testsuite/gcc.target/i386/cmov7.c +++ b/gcc/testsuite/gcc.target/i386/cmov7.c @@ -10,7 +10,7 @@ (set (reg:DF) (float_extend:DF (mem:SF (symbol_ref...)))). */ double -sgn (double __x) +foo (double __x) { - return __x >= 0.0 ? 1.0 : -1.0; + return __x >= 1.0 ? 0.0 : -1.0; } diff --git a/gcc/testsuite/gcc.target/i386/interrupt-5.c b/gcc/testsuite/gcc.target/i386/interrupt-5.c index 803c0636299..5742b6f4743 100644 --- a/gcc/testsuite/gcc.target/i386/interrupt-5.c +++ b/gcc/testsuite/gcc.target/i386/interrupt-5.c @@ -7,12 +7,21 @@ extern void link_error (void); typedef unsigned int uword_t __attribute__ ((mode (__word__))); +struct interrupt_frame +{ + uword_t ip; + uword_t cs; + uword_t flags; + uword_t sp; + uword_t ss; +}; + __attribute__ ((used, interrupt)) void -foo (void *frame, uword_t error) +foo (struct interrupt_frame *frame, uword_t error) { void *ra = __builtin_return_address (0); - if ((uintptr_t) ra != (uintptr_t) error) + if ((uintptr_t) ra != (uintptr_t) frame->ip) link_error (); } diff --git a/gcc/testsuite/gcc.target/i386/mvc2.c b/gcc/testsuite/gcc.target/i386/mvc2.c index 9635ec83fac..34a777c1d5e 100644 --- a/gcc/testsuite/gcc.target/i386/mvc2.c +++ b/gcc/testsuite/gcc.target/i386/mvc2.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-ifunc "" } */ __attribute__((target_clones("avx","arch=slm","arch=core-avx2"))) int foo (); diff --git a/gcc/testsuite/gcc.target/i386/mvc3.c b/gcc/testsuite/gcc.target/i386/mvc3.c index f940cdbbf55..1c7755fabbe 100644 --- a/gcc/testsuite/gcc.target/i386/mvc3.c +++ b/gcc/testsuite/gcc.target/i386/mvc3.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-ifunc "" } */ __attribute__((target_clones("avx","arch=slm","arch=core-avx2"))) int foo (); /* { dg-error "default target was not set" } */ diff --git a/gcc/testsuite/gcc.target/i386/mvc6.c b/gcc/testsuite/gcc.target/i386/mvc6.c index d584f573328..af631394980 100644 --- a/gcc/testsuite/gcc.target/i386/mvc6.c +++ b/gcc/testsuite/gcc.target/i386/mvc6.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-ifunc "" } */ /* { dg-options "-O3" } */ /* { dg-final { scan-assembler "vpshufb" } } */ /* { dg-final { scan-assembler "punpcklbw" } } */ diff --git a/gcc/testsuite/gcc.target/i386/naked-1.c b/gcc/testsuite/gcc.target/i386/naked-1.c new file mode 100644 index 00000000000..440dbe9ee7a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/naked-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +/* Verify that __attribute__((naked)) produces a naked function + that does not use ret to return but traps at the end. */ +void +__attribute__((naked)) +foo (void) +{ + __asm__ ("# naked"); +} +/* { dg-final { scan-assembler "# naked" } } */ +/* { dg-final { scan-assembler "ud2" } } */ +/* { dg-final { scan-assembler-not "ret" } } */ diff --git a/gcc/testsuite/gcc.target/i386/naked-2.c b/gcc/testsuite/gcc.target/i386/naked-2.c new file mode 100644 index 00000000000..adcd7121541 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/naked-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +/* Verify that __attribute__((naked)) produces a naked function + that does not construct a frame. */ +void +__attribute__((naked)) +foo (void) +{ + __asm__ ("# naked"); +} +/* { dg-final { scan-assembler "# naked" } } */ +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ diff --git a/gcc/testsuite/gcc.target/i386/naked-3.c b/gcc/testsuite/gcc.target/i386/naked-3.c new file mode 100644 index 00000000000..845300d6e4a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/naked-3.c @@ -0,0 +1,39 @@ +/* { dg-do run { target *-*-linux* *-*-gnu* } } */ +/* { dg-options "-O2" } */ + +#include <unistd.h> +#include <signal.h> +#include <stdlib.h> + +int data; + +/* Verify that naked function traps at the end. */ + +void +__attribute__((naked, noinline, noclone)) +naked (void) +{ + if (data == 0x12345678) + return; + asm ("ret"); +} + +void handler (int i) +{ + exit (0); +} + +int main () +{ + struct sigaction s; + + sigemptyset (&s.sa_mask); + s.sa_handler = handler; + s.sa_flags = 0; + sigaction (SIGILL, &s, NULL); + + data = 0x12345678; + naked (); + + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr48723.c b/gcc/testsuite/gcc.target/i386/pr48723.c index ad102090e9f..222c075fbf7 100644 --- a/gcc/testsuite/gcc.target/i386/pr48723.c +++ b/gcc/testsuite/gcc.target/i386/pr48723.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-fstack-check -mavx" } */ struct S0 diff --git a/gcc/testsuite/gcc.target/i386/pr55672.c b/gcc/testsuite/gcc.target/i386/pr55672.c index 6f1c898c748..f7b0d717e01 100644 --- a/gcc/testsuite/gcc.target/i386/pr55672.c +++ b/gcc/testsuite/gcc.target/i386/pr55672.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-stack-check "generic" } */ /* { dg-options "-O -fstack-check=generic" } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr67265-2.c b/gcc/testsuite/gcc.target/i386/pr67265-2.c index a9f2eb460ef..690a7845557 100644 --- a/gcc/testsuite/gcc.target/i386/pr67265-2.c +++ b/gcc/testsuite/gcc.target/i386/pr67265-2.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-O -fstack-check" } */ void foo (int n) diff --git a/gcc/testsuite/gcc.target/i386/pr67265.c b/gcc/testsuite/gcc.target/i386/pr67265.c index 7827685fe5f..2671acc043a 100644 --- a/gcc/testsuite/gcc.target/i386/pr67265.c +++ b/gcc/testsuite/gcc.target/i386/pr67265.c @@ -2,6 +2,7 @@ /* Reduced testcase by Johannes Dewender <gnu@JonnyJD.net> */ /* { dg-do compile } */ +/* { dg-require-stack-check "" } */ /* { dg-options "-O -fstack-check -fPIC" } */ int a, b, c, d, e; diff --git a/gcc/testsuite/gcc.target/i386/pr69255-2.c b/gcc/testsuite/gcc.target/i386/pr69255-2.c index ebe6828e188..af3be6c31a2 100644 --- a/gcc/testsuite/gcc.target/i386/pr69255-2.c +++ b/gcc/testsuite/gcc.target/i386/pr69255-2.c @@ -12,7 +12,8 @@ __attribute__ ((__vector_size__ (16))) int b; void foo (const long long *p) { - __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */ + volatile __attribute__ ((__vector_size__ (32))) long long c; + c = __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */ /* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } .-1 } */ /* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } .-2 } */ } diff --git a/gcc/testsuite/gcc.target/i386/pr79793-1.c b/gcc/testsuite/gcc.target/i386/pr79793-1.c new file mode 100644 index 00000000000..a382fe9c5e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79793-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -mgeneral-regs-only" } */ + +void + __attribute__ ((interrupt)) +fn1 (void *frame) +{ + char fxsave_region [512] __attribute__((aligned(16))); + __builtin_ia32_fxsave64 (fxsave_region); +} + +/* { dg-final { scan-assembler-times "sub\[lq\]\[\t \]*\\\$400,\[\t \]*%\[re\]sp" 1 } } */ +/* { dg-final { scan-assembler-times "fxsave64\[\t \]*-120\\(%\[re\]sp\\)" 1 } } */ +/* { dg-final { scan-assembler-times "add\[lq\]\[\t \]*\\\$400,\[\t \]*%\[re\]sp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr79793-2.c b/gcc/testsuite/gcc.target/i386/pr79793-2.c new file mode 100644 index 00000000000..f6ae5aed33a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr79793-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -mgeneral-regs-only" } */ + +typedef unsigned int uword_t __attribute__ ((mode (__word__))); + +void + __attribute__ ((interrupt)) +fn1 (void *frame, uword_t error) +{ + char fxsave_region [512] __attribute__((aligned(16))); + __builtin_ia32_fxsave64 (fxsave_region); +} + +/* { dg-final { scan-assembler-times "sub\[lq\]\[\t \]*\\\$392,\[\t \]*%\[re\]sp" 1 } } */ +/* { dg-final { scan-assembler-times "fxsave64\[\t \]*-120\\(%\[re\]sp\\)" 1 } } */ +/* { dg-final { scan-assembler-times "add\[lq\]\[\t \]*\\\$400,\[\t \]*%\[re\]sp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr80569.c b/gcc/testsuite/gcc.target/i386/pr80569.c new file mode 100644 index 00000000000..8e11c40bb08 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80569.c @@ -0,0 +1,9 @@ +/* PR target/80569 */ +/* { dg-do assemble } */ +/* { dg-options "-O2 -m16 -march=haswell" } */ + +void load_kernel(void *setup_addr) +{ + unsigned int seg = (unsigned int)setup_addr >> 4; + asm("movl %0, %%es" : : "r"(seg)); +} diff --git a/gcc/testsuite/gcc.target/i386/pr80833-3.c b/gcc/testsuite/gcc.target/i386/pr80833-3.c new file mode 100644 index 00000000000..6d5b8bb6b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80833-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw -mtune=intel" } */ + +__int128 test (__int128 a) +{ + asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15"); + return a; +} + +/* { dg-final { scan-assembler "pinsrq" } } */ +/* { dg-final { scan-assembler "pextrq" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81128.c b/gcc/testsuite/gcc.target/i386/pr81128.c new file mode 100644 index 00000000000..90a567ad690 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81128.c @@ -0,0 +1,65 @@ +/* PR ipa/81128 */ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-ifunc "" } */ + + +#include <stdio.h> +#include <stdlib.h> +#include <time.h> + +int resolver_fn = 0; +int resolved_fn = 0; + +static inline void +do_it_right_at_runtime_A () +{ + resolved_fn++; +} + +static inline void +do_it_right_at_runtime_B () +{ + resolved_fn++; +} + +static inline void do_it_right_at_runtime (void); + +void do_it_right_at_runtime (void) + __attribute__ ((ifunc ("resolve_do_it_right_at_runtime"))); + +static void (*resolve_do_it_right_at_runtime (void)) (void) +{ + srand (time (NULL)); + int r = rand (); + resolver_fn++; + + /* Use intermediate variable to get a warning for non-matching + * prototype. */ + typeof(do_it_right_at_runtime) *func; + if (r & 1) + func = do_it_right_at_runtime_A; + else + func = do_it_right_at_runtime_B; + + return (void *) func; +} + +int +main (void) +{ + const unsigned int ITERS = 10; + + for (int i = ITERS; i > 0; i--) + { + do_it_right_at_runtime (); + } + + if (resolver_fn != 1) + __builtin_abort (); + + if (resolved_fn != 10) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81214.c b/gcc/testsuite/gcc.target/i386/pr81214.c new file mode 100644 index 00000000000..2584decdb3c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81214.c @@ -0,0 +1,14 @@ +/* PR ipa/81214. */ +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ + +__attribute__((target_clones("avx","arch=slm","arch=core-avx2","default"))) +int +foo () +{ + return -2; +} + +/* { dg-final { scan-assembler "\t.globl\tfoo" } } */ +/* { dg-final { scan-assembler "foo.resolver:" } } */ +/* { dg-final { scan-assembler "foo, @gnu_indirect_function" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81225.c b/gcc/testsuite/gcc.target/i386/pr81225.c new file mode 100644 index 00000000000..db95e941c14 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81225.c @@ -0,0 +1,14 @@ +/* PR target/81225 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512ifma -O3 -ffloat-store" } */ + +long a[24]; +float b[4], c[24]; +int d; + +void +foo () +{ + for (d = 0; d < 24; d++) + c[d] = (float) d ? : b[a[d]]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81294-1.c b/gcc/testsuite/gcc.target/i386/pr81294-1.c new file mode 100644 index 00000000000..6a15ed0a410 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81294-1.c @@ -0,0 +1,29 @@ +/* PR target/81294 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include <x86intrin.h> + +int +main () +{ + volatile unsigned char c; + unsigned int x; + volatile unsigned int y, sum_ref; + + c = 0; + x = 1; + y = 0; + sum_ref = 0x0; + + /* X = 0x00000001, Y = 0x00000000, C = 0. */ + c = _subborrow_u32 (c, y, x, &x); + /* X = 0xFFFFFFFF, Y = 0x00000000, C = 1. */ + c = _subborrow_u32 (c, y, x, &x); + /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 1. */ + + if (x != sum_ref) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81294-2.c b/gcc/testsuite/gcc.target/i386/pr81294-2.c new file mode 100644 index 00000000000..3e3bdb44139 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81294-2.c @@ -0,0 +1,28 @@ +/* PR target/81294 */ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +#include <x86intrin.h> + +int main () +{ + volatile unsigned char c; + unsigned long long x; + volatile unsigned long long y, sum_ref; + + c = 0; + x = 1LL; + y = 0LL; + sum_ref = 0x0LL; + + /* X = 0x0000000000000001, Y = 0x0000000000000000, C = 0. */ + c = _subborrow_u64 (c, y, x, &x); + /* X = 0xFFFFFFFFFFFFFFFF, Y = 0x0000000000000000, C = 1. */ + c = _subborrow_u64 (c, y, x, &x); + /* X = 0x0000000000000000, Y = 0x0000000000000000, C = 1. */ + + if (x != sum_ref) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81300.c b/gcc/testsuite/gcc.target/i386/pr81300.c new file mode 100644 index 00000000000..11eb55fed8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81300.c @@ -0,0 +1,30 @@ +/* PR target/81300 */ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +int +__attribute__((noinline, noclone)) +foo (void) +{ + unsigned long long _discard = 0, zero = 0, maxull = 0; + unsigned char zero1 = __builtin_ia32_addcarryx_u64 (0, 0, 0, &_discard); + unsigned char zero2 = __builtin_ia32_addcarryx_u64 (zero1, 0, 0, &zero); + __builtin_ia32_sbb_u64 (0x0, 2, -1, &_discard); + unsigned char one = __builtin_ia32_sbb_u64 (0, zero, 1, &maxull); + unsigned long long x = __builtin_ia32_sbb_u64 (one, zero2, 0, &_discard); + + unsigned long long z1 = 0; + __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z1) : "r" (x)); + unsigned long long z2 = 3; + __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z2) : "r" (x)); + + return 1 - (z1 | z2); +} + +int main () +{ + if (foo ()) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81313-1.c b/gcc/testsuite/gcc.target/i386/pr81313-1.c new file mode 100644 index 00000000000..f7650035cac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81313-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-accumulate-outgoing-args -mincoming-stack-boundary=4 -mpreferred-stack-boundary=6" } */ + +extern void foo (void); + +void +bar (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-not "lea\[lq\]?\[\\t \]*\[0-9\]*\\(%\[er\]sp\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81313-2.c b/gcc/testsuite/gcc.target/i386/pr81313-2.c new file mode 100644 index 00000000000..2cdc645dbcc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81313-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2 -mno-accumulate-outgoing-args -mincoming-stack-boundary=4 -mpreferred-stack-boundary=6 -mno-iamcu" } */ + +extern void foo (int, int, int); + +void +bar (void) +{ + foo (1, 2, 3); +} + +/* { dg-final { scan-assembler "lea\[l\]?\[\\t \]*\[0-9\]*\\(%esp\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81313-3.c b/gcc/testsuite/gcc.target/i386/pr81313-3.c new file mode 100644 index 00000000000..9c1b2326616 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81313-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2 -mno-accumulate-outgoing-args -mincoming-stack-boundary=4 -mpreferred-stack-boundary=6" } */ + +extern void foo (int, int, int) __attribute__ ((regparm(3))); + +void +bar (int i1, int i2, int i3, int i4) +{ + foo (i1, i2, i3); +} + +/* { dg-final { scan-assembler-not "lea\[l\]?\[\\t \]*\[0-9\]*\\(%esp\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81313-4.c b/gcc/testsuite/gcc.target/i386/pr81313-4.c new file mode 100644 index 00000000000..bad0b3c27db --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81313-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-accumulate-outgoing-args -mincoming-stack-boundary=4 -mpreferred-stack-boundary=6" } */ + +extern void foo (int, int, int, int, int, int, int); + +void +bar (void) +{ + foo (1, 2, 3, 4, 5, 6, 7); +} + +/* { dg-final { scan-assembler "lea\[lq\]?\[\\t \]*\[0-9\]*\\(%\[er\]sp\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81313-5.c b/gcc/testsuite/gcc.target/i386/pr81313-5.c new file mode 100644 index 00000000000..51a543ca57e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81313-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-accumulate-outgoing-args -mincoming-stack-boundary=4 -mpreferred-stack-boundary=6" } */ + +extern void foo (int, int, int, int, int, int); + +void +bar (int i1, int i2, int i3, int i4, int i5, int i6, int i7) +{ + foo (i1, i2, i3, i4, i5, i6); +} + +/* { dg-final { scan-assembler-not "lea\[lq\]?\[\\t \]*\[0-9\]*\\(%\[er\]sp\\)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81375.c b/gcc/testsuite/gcc.target/i386/pr81375.c new file mode 100644 index 00000000000..256a79df719 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81375.c @@ -0,0 +1,8 @@ +/* PR target/81375 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-mno-80387 -mno-sse -mfpmath=sse" } */ + +float foo (float a, float b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/i386/pr81471.c b/gcc/testsuite/gcc.target/i386/pr81471.c new file mode 100644 index 00000000000..68b4497c9f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81471.c @@ -0,0 +1,13 @@ +/* PR target/81471 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +static inline unsigned int rotl (unsigned int x, int k) +{ + return (x << k) | (x >> (32 - k)); +} + +unsigned long long test (unsigned int z) +{ + return rotl (z, 55); +} diff --git a/gcc/testsuite/gcc.target/i386/pr81502.c b/gcc/testsuite/gcc.target/i386/pr81502.c new file mode 100644 index 00000000000..d28791aacd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81502.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +#define SIZE (sizeof (void *)) + +static int foo(unsigned char (*foo)[SIZE]) +{ + __m128i acc = _mm_set_epi32(0, 0, 0, 0); + size_t i = 0; + for(; i + sizeof(__m128i) <= SIZE; i += sizeof(__m128i)) { + __m128i word; + __builtin_memcpy(&word, foo + i, sizeof(__m128i)); + acc = _mm_add_epi32(word, acc); + } + if (i != SIZE) { + __m128i word = _mm_set_epi32(0, 0, 0, 0); + __builtin_memcpy(&word, foo + i, SIZE - i); // (1) + acc = _mm_add_epi32(word, acc); + } + int res; + __builtin_memcpy(&res, &acc, sizeof(res)); + return res; +} + +int bar(void *ptr) +{ + unsigned char buf[SIZE]; + __builtin_memcpy(buf, &ptr, SIZE); + return foo((unsigned char(*)[SIZE])buf); +} + +/* { dg-final { scan-assembler-times "mov" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr81563.c b/gcc/testsuite/gcc.target/i386/pr81563.c new file mode 100644 index 00000000000..ebfd583daf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81563.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2 -maccumulate-outgoing-args -mincoming-stack-boundary=2 -mpreferred-stack-boundary=3 -mregparm=3 -mtune-ctrl=epilogue_using_move" } */ + +extern void bar (long long int, int); + +long long int +fn1 (long long int x) +{ + bar (x, 1); + return x; +} + +/* { dg-final { scan-assembler-times "movl\[\\t \]*-8\\(%ebp\\),\[\\t \]*%esi" 1 } } */ +/* { dg-final { scan-assembler-times "movl\[\\t \]*-4\\(%ebp\\),\[\\t \]*%edi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 79879d7cc16..c5c43b12611 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -250,11 +250,15 @@ #define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8) #define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8) #define __builtin_ia32_getexpsd128_round(A, B, C) __builtin_ia32_getexpsd128_round(A, B, 4) +#define __builtin_ia32_getexpsd_mask_round(A, B, C, D, E) __builtin_ia32_getexpsd_mask_round(A, B, C, D, 4) #define __builtin_ia32_getexpss128_round(A, B, C) __builtin_ia32_getexpss128_round(A, B, 4) +#define __builtin_ia32_getexpss_mask_round(A, B, C, D, E) __builtin_ia32_getexpss_mask_round(A, B, C, D, 4) #define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantsd_round(A, B, C, D) __builtin_ia32_getmantsd_round(A, B, 1, 4) +#define __builtin_ia32_getmantsd_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsd_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_getmantss_round(A, B, C, D) __builtin_ia32_getmantss_round(A, B, 1, 4) +#define __builtin_ia32_getmantss_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantss_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E) #define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E) diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 547314aef07..c2a19b3ccef 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -244,7 +244,9 @@ test_2 (_mm512_maskz_extractf64x4_pd, __m256d, __mmask8, __m512d, 1) test_2 (_mm512_maskz_extracti32x4_epi32, __m128i, __mmask8, __m512i, 1) test_2 (_mm512_maskz_extracti64x4_epi64, __m256i, __mmask8, __m512i, 1) test_2 (_mm512_maskz_getexp_round_pd, __m512d, __mmask8, __m512d, 8) +test_3 (_mm_maskz_getexp_round_sd, __m128d, __mmask8, __m128d, __m128d, 8) test_2 (_mm512_maskz_getexp_round_ps, __m512, __mmask16, __m512, 8) +test_3 (_mm_maskz_getexp_round_ss, __m128, __mmask8, __m128, __m128, 8) test_2y (_mm512_maskz_getmant_round_pd, __m512d, __mmask8, __m512d, 1, 1, 8) test_2y (_mm512_maskz_getmant_round_ps, __m512, __mmask16, __m512, 1, 1, 8) test_2 (_mm512_maskz_permute_pd, __m512d, __mmask8, __m512d, 1) @@ -300,7 +302,11 @@ test_2 (_mm_div_round_ss, __m128, __m128, __m128, 9) test_2 (_mm_getexp_round_sd, __m128d, __m128d, __m128d, 8) test_2 (_mm_getexp_round_ss, __m128, __m128, __m128, 8) test_2y (_mm_getmant_round_sd, __m128d, __m128d, __m128d, 1, 1, 8) +test_4y (_mm_mask_getmant_round_sd, __m128d, __m128d, __mmask8, __m128d, __m128d, 1, 1, 8) +test_3y (_mm_maskz_getmant_round_sd, __m128d, __mmask8, __m128d, __m128d, 1, 1, 8) test_2y (_mm_getmant_round_ss, __m128, __m128, __m128, 1, 1, 8) +test_4y (_mm_mask_getmant_round_ss, __m128, __m128, __mmask8, __m128, __m128, 1, 1, 8) +test_3y (_mm_maskz_getmant_round_ss, __m128, __mmask8, __m128, __m128, 1, 1, 8) test_2 (_mm_mul_round_sd, __m128d, __m128d, __m128d, 9) test_2 (_mm_mul_round_ss, __m128, __m128, __m128, 9) test_2 (_mm_scalef_round_sd, __m128d, __m128d, __m128d, 9) @@ -356,7 +362,9 @@ test_3 (_mm512_mask_extractf64x4_pd, __m256d, __m256d, __mmask8, __m512d, 1) test_3 (_mm512_mask_extracti32x4_epi32, __m128i, __m128i, __mmask8, __m512i, 1) test_3 (_mm512_mask_extracti64x4_epi64, __m256i, __m256i, __mmask8, __m512i, 1) test_3 (_mm512_mask_getexp_round_pd, __m512d, __m512d, __mmask8, __m512d, 8) +test_4 (_mm_mask_getexp_round_sd, __m128d, __m128d, __mmask8, __m128d, __m128d, 8) test_3 (_mm512_mask_getexp_round_ps, __m512, __m512, __mmask16, __m512, 8) +test_4 (_mm_mask_getexp_round_ss, __m128, __m128, __mmask8, __m128, __m128, 8) test_3y (_mm512_mask_getmant_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 1, 8) test_3y (_mm512_mask_getmant_round_ps, __m512, __m512, __mmask16, __m512, 1, 1, 8) test_3 (_mm512_mask_permute_pd, __m512d, __m512d, __mmask8, __m512d, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index b8a35d11c45..cd8945be1cb 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -399,7 +399,9 @@ test_2 (_mm512_maskz_extracti64x4_epi64, __m256i, __mmask8, __m512i, 1) test_2 (_mm512_maskz_getexp_round_pd, __m512d, __mmask8, __m512d, 8) test_2 (_mm512_maskz_getexp_round_ps, __m512, __mmask16, __m512, 8) test_2y (_mm512_maskz_getmant_round_pd, __m512d, __mmask8, __m512d, 1, 1, 8) +test_3y (_mm_maskz_getmant_round_sd, __m128d, __mmask8, __m128d, __m128d, 1, 1, 8) test_2y (_mm512_maskz_getmant_round_ps, __m512, __mmask16, __m512, 1, 1, 8) +test_3y (_mm_maskz_getmant_round_ss, __m128, __mmask8, __m128, __m128, 1, 1, 8) test_2 (_mm512_maskz_permute_pd, __m512d, __mmask8, __m512d, 1) test_2 (_mm512_maskz_permute_ps, __m512, __mmask16, __m512, 1) test_2 (_mm512_maskz_permutex_epi64, __m512i, __mmask8, __m512i, 1) @@ -491,7 +493,9 @@ test_3 (_mm512_mask_extracti64x4_epi64, __m256i, __m256i, __mmask8, __m512i, 1) test_3 (_mm512_mask_getexp_round_pd, __m512d, __m512d, __mmask8, __m512d, 8) test_3 (_mm512_mask_getexp_round_ps, __m512, __m512, __mmask16, __m512, 8) test_3y (_mm512_mask_getmant_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 1, 8) +test_4y (_mm_mask_getmant_round_sd, __m128d, __m128d, __mmask8, __m128d, __m128d, 1, 1, 8) test_3y (_mm512_mask_getmant_round_ps, __m512, __m512, __mmask16, __m512, 1, 1, 8) +test_4y (_mm_mask_getmant_round_ss, __m128, __m128, __mmask8, __m128, __m128, 1, 1, 8) test_3 (_mm512_mask_permute_pd, __m512d, __m512d, __mmask8, __m512d, 1) test_3 (_mm512_mask_permute_ps, __m512, __m512, __mmask16, __m512, 1) test_3 (_mm512_mask_permutex_epi64, __m512i, __m512i, __mmask8, __m512i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 96c663b64d3..fc339a51e63 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -251,11 +251,15 @@ #define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8) #define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8) #define __builtin_ia32_getexpsd128_round(A, B, C) __builtin_ia32_getexpsd128_round(A, B, 4) +#define __builtin_ia32_getexpsd_mask_round(A, B, C, D, E) __builtin_ia32_getexpsd_mask_round(A, B, C, D, 4) #define __builtin_ia32_getexpss128_round(A, B, C) __builtin_ia32_getexpss128_round(A, B, 4) +#define __builtin_ia32_getexpss_mask_round(A, B, C, D, E) __builtin_ia32_getexpss_mask_round(A, B, C, D, 4) #define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8) #define __builtin_ia32_getmantsd_round(A, B, C, D) __builtin_ia32_getmantsd_round(A, B, 1, 4) +#define __builtin_ia32_getmantsd_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsd_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_getmantss_round(A, B, C, D) __builtin_ia32_getmantss_round(A, B, 1, 4) +#define __builtin_ia32_getmantss_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantss_mask_round(A, B, 1, W, U, 4) #define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E) #define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E) diff --git a/gcc/testsuite/gcc.target/i386/testimm-10.c b/gcc/testsuite/gcc.target/i386/testimm-10.c index c2bf0dbabd1..d0e9b42f2fe 100644 --- a/gcc/testsuite/gcc.target/i386/testimm-10.c +++ b/gcc/testsuite/gcc.target/i386/testimm-10.c @@ -191,5 +191,9 @@ test4bit (void) { m512 = _mm512_maskz_getmant_ps (mmask16, m512, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ m128d = _mm_getmant_sd (m128d, m128d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ + m128d = _mm_mask_getmant_sd (m128d, mmask8, m128d, m128d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ + m128d = _mm_maskz_getmant_sd (mmask8, m128d, m128d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ m128 = _mm_getmant_ss (m128, m128, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ + m128 = _mm_mask_getmant_ss (m128, mmask8, m128, m128, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ + m128 = _mm_maskz_getmant_ss (mmask8, m128, m128, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */ } diff --git a/gcc/testsuite/gcc.target/i386/testround-1.c b/gcc/testsuite/gcc.target/i386/testround-1.c index 2c1338164f5..d5ab95c208e 100644 --- a/gcc/testsuite/gcc.target/i386/testround-1.c +++ b/gcc/testsuite/gcc.target/i386/testround-1.c @@ -249,7 +249,11 @@ test_round (void) m128d = _mm_cvt_roundss_sd (m128d, m128, 7); /* { dg-error "incorrect rounding operand" } */ m128 = _mm_getexp_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_mask_getexp_round_ss (m128, mmask8, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_maskz_getexp_round_ss (mmask8, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */ m128d = _mm_getexp_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_mask_getexp_round_sd (m128d, mmask8, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_maskz_getexp_round_sd (mmask8, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_getexp_round_ps (m512, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_mask_getexp_round_ps (m512, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_maskz_getexp_round_ps (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */ @@ -263,7 +267,11 @@ test_round (void) m512 = _mm512_mask_getmant_round_ps (m512, mmask16, m512, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_maskz_getmant_round_ps (mmask16, m512, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ m128d = _mm_getmant_round_sd (m128d, m128d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_mask_getmant_round_sd (m128d, mmask8, m128d, m128d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_maskz_getmant_round_sd (mmask8, m128d, m128d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ m128 = _mm_getmant_round_ss (m128, m128, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_mask_getmant_round_ss (m128, mmask8, m128, m128, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_maskz_getmant_round_ss (mmask8, m128, m128, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_roundscale_round_ps (m512, 4, 7); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_mask_roundscale_round_ps (m512, mmask16, m512, 4, 7); /* { dg-error "incorrect rounding operand" } */ @@ -524,7 +532,11 @@ test_sae_only (void) m128d = _mm_cvt_roundss_sd (m128d, m128, 3); /* { dg-error "incorrect rounding operand" } */ m128 = _mm_getexp_round_ss (m128, m128, 3); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_mask_getexp_round_ss (m128, mmask8, m128, m128, 3); /* { dg-error "incorrect rounding operand" } */ + m128 = _mm_maskz_getexp_round_ss (mmask8, m128, m128, 3); /* { dg-error "incorrect rounding operand" } */ m128d = _mm_getexp_round_sd (m128d, m128d, 3); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_mask_getexp_round_sd (m128d, mmask8, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */ + m128d = _mm_maskz_getexp_round_sd (mmask8, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_getexp_round_ps (m512, 3); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_mask_getexp_round_ps (m512, mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */ m512 = _mm512_maskz_getexp_round_ps (mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */ diff --git a/gcc/testsuite/gcc.target/i386/umod-3.c b/gcc/testsuite/gcc.target/i386/umod-3.c index e1fb988263a..609ab520712 100644 --- a/gcc/testsuite/gcc.target/i386/umod-3.c +++ b/gcc/testsuite/gcc.target/i386/umod-3.c @@ -9,9 +9,11 @@ int main () { unsigned char cy; - - cy = cx / 6; if (cy != 1) exit (1); - cy = cx % 6; if (cy != 1) exit (1); + unsigned char cz = 1; + asm ("" : "+q" (cz)); + + cy = cx / 6; if (cy != cz) exit (1); + cy = cx % 6; if (cy != cz) exit (1); exit(0); } diff --git a/gcc/testsuite/gcc.target/i386/vect-insert-1.c b/gcc/testsuite/gcc.target/i386/vect-insert-1.c new file mode 100644 index 00000000000..55cc52334c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-insert-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -fdump-tree-ccp1" } */ + +typedef int v4si __attribute__((vector_size(16))); + +float f; + +v4si foo (v4si a) +{ + __builtin_memcpy ((char *)&a + 4, &f, 4); + return a; +} + +/* { dg-final { scan-tree-dump "Now a gimple register: a" "ccp1" } } */ +/* { dg-final { scan-tree-dump "BIT_INSERT_EXPR <a" "ccp1" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/decl-init.c b/gcc/testsuite/gcc.target/nvptx/decl-init.c index e9af9075756..23008fb209c 100644 --- a/gcc/testsuite/gcc.target/nvptx/decl-init.c +++ b/gcc/testsuite/gcc.target/nvptx/decl-init.c @@ -37,7 +37,7 @@ struct five five2[2] = {{12, 13}, {14, 15}}; /* { dg-final { scan-assembler ".align 1 .u8 five2\\\[10\\\] = { 12, 13, 0, 0, 0, 14, 15, 0, 0, 0 };" } } */ int __attribute__((vector_size(16))) vi = {16, 17, 18, 19}; -/* { dg-final { scan-assembler ".align 8 .u32 vi\\\[4\\\] = { 16, 17, 18, 19 };" } } */ +/* { dg-final { scan-assembler ".align 16 .u32 vi\\\[4\\\] = { 16, 17, 18, 19 };" } } */ typedef int __attribute ((mode(TI))) ti_t; diff --git a/gcc/testsuite/gcc.target/nvptx/slp-2-run.c b/gcc/testsuite/gcc.target/nvptx/slp-2-run.c new file mode 100644 index 00000000000..f9841a6b11a --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/slp-2-run.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-slp-vectorize" } */ + +#include "slp-2.c" + +int +main(void) +{ + unsigned int i; + for (i = 0; i < 1000; i += 1) + { + p[i] = i; + p2[i] = 0; + } + + foo (); + + for (i = 0; i < 1000; i += 1) + if (p2[i] != i) + return 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/nvptx/slp-2.c b/gcc/testsuite/gcc.target/nvptx/slp-2.c new file mode 100644 index 00000000000..66394918d63 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/slp-2.c @@ -0,0 +1,25 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-slp-vectorize -save-temps" } */ + +long long int p[1000] __attribute__((aligned(16))); +long long int p2[1000] __attribute__((aligned(16))); + +void __attribute__((noinline, noclone)) +foo () +{ + long long int a, b; + + unsigned int i; + for (i = 0; i < 1000; i += 2) + { + a = p[i]; + b = p[i+1]; + + p2[i] = a; + p2[i+1] = b; + } +} + +/* { dg-final { scan-assembler "ld.v2.u64" } } */ +/* { dg-final { scan-assembler "st.v2.u64" } } */ + diff --git a/gcc/testsuite/gcc.target/nvptx/slp-run.c b/gcc/testsuite/gcc.target/nvptx/slp-run.c new file mode 100644 index 00000000000..dedec471bb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/slp-run.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-slp-vectorize" } */ + +#include "slp.c" + +int +main(void) +{ + unsigned int i; + for (i = 0; i < 1000; i += 1) + { + p[i] = i; + p2[i] = 0; + } + + foo (); + + for (i = 0; i < 1000; i += 1) + if (p2[i] != i) + return 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/nvptx/slp.c b/gcc/testsuite/gcc.target/nvptx/slp.c new file mode 100644 index 00000000000..5dee147af9c --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/slp.c @@ -0,0 +1,25 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-slp-vectorize -save-temps" } */ + +int p[1000] __attribute__((aligned(8))); +int p2[1000] __attribute__((aligned(8))); + +void __attribute__((noinline, noclone)) +foo () +{ + int a, b; + + unsigned int i; + for (i = 0; i < 1000; i += 2) + { + a = p[i]; + b = p[i+1]; + + p2[i] = a; + p2[i+1] = b; + } +} + +/* { dg-final { scan-assembler "ld.v2.u32" } } */ +/* { dg-final { scan-assembler "st.v2.u32" } } */ + diff --git a/gcc/testsuite/gcc.target/nvptx/v2di.c b/gcc/testsuite/gcc.target/nvptx/v2di.c new file mode 100644 index 00000000000..f63ad35d816 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/v2di.c @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -save-temps" } */ + +typedef long long int __v2di __attribute__((__vector_size__(16))); + +#define TYPE __v2di +#include "vec.inc" + +/* { dg-final { scan-assembler ".reg\\.v2\\.u64" } } */ +/* { dg-final { scan-assembler "ld\\.v2\\.u64" } } */ +/* { dg-final { scan-assembler "st\\.v2\\.u64" } } */ +/* { dg-final { scan-assembler "mov\\.v2\\.u64.*\\{ 1, 2 \\}" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/v2si-cvt.c b/gcc/testsuite/gcc.target/nvptx/v2si-cvt.c new file mode 100644 index 00000000000..73f86bcfa9e --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/v2si-cvt.c @@ -0,0 +1,39 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -save-temps" } */ + +typedef int __v2si __attribute__((__vector_size__(8))); + +int __attribute__((unused)) +vector_cvt (__v2si arg) +{ + __v2si val4 = arg; + char *p = (char*)&val4; + + if (p[0] != 1) + return 1; + if (p[1] != 2) + return 1; + if (p[2] != 3) + return 1; + + return 0; +} + +int +vector_cvt_2 (__v2si val, __v2si val2) +{ + char *p = (char*)&val; + char *p2 = (char*)&val2; + + if (p[0] != p2[0]) + return 1; + if (p[4] != p2[4]) + return 1; + + return 0; +} + +/* We want to test for 'mov.t' here, but given PR80845 we test for cvt.t.t + instead. + { dg-final { scan-assembler "(?n)cvt\\.u32\\.u32.*\\.x" } } */ +/* { dg-final { scan-assembler "(?n)cvt\\.u16\\.u32.*\\.x" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/v2si-run.c b/gcc/testsuite/gcc.target/nvptx/v2si-run.c new file mode 100644 index 00000000000..5821a5a95d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/v2si-run.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "v2si.c" + +void __attribute__((noinline, noclone)) +init_val ( __v2si *p) +{ + char *p2 = (char*)p; + p2[0] = 8; + p2[1] = 7; + p2[2] = 6; + p2[3] = 5; + p2[4] = 4; + p2[5] = 3; + p2[6] = 2; + p2[7] = 1; +} + +int +main (void) +{ + { + __v2si val; + __v2si val2; + __v2si val3; + + init_val(&val); + + /* Copy val to val2. */ + vector_store (&val2, val); + + /* Copy val2 to val3. */ + val3 = vector_load (&val2); + + /* Compare val to val3. */ + { + char *p = (char*)&val; + char *p2 = (char*)&val3; + + if (p[0] != p2[0]) + return 1; + if (p[1] != p2[1]) + return 1; + if (p[2] != p2[2]) + return 1; + if (p[3] != p2[3]) + return 1; + if (p[4] != p2[4]) + return 1; + if (p[5] != p2[5]) + return 1; + if (p[6] != p2[6]) + return 1; + if (p[7] != p2[7]) + return 1; + } + } + + { + __v2si val4 = vector_const (); + char *p = (char*)&val4; + + if (p[0] != 1) + return 1; + if (p[1] != 0) + return 1; + if (p[2] != 0) + return 1; + if (p[3] != 0) + return 1; + if (p[4] != 2) + return 1; + if (p[5] != 0) + return 1; + if (p[6] != 0) + return 1; + if (p[7] != 0) + return 1; + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/nvptx/v2si.c b/gcc/testsuite/gcc.target/nvptx/v2si.c new file mode 100644 index 00000000000..ce423d82c2c --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/v2si.c @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -save-temps" } */ + +typedef int __v2si __attribute__((__vector_size__(8))); + +#define TYPE __v2si +#include "vec.inc" + +/* { dg-final { scan-assembler ".reg\\.v2\\.u32" } } */ +/* { dg-final { scan-assembler "ld\\.v2\\.u32" } } */ +/* { dg-final { scan-assembler "st\\.v2\\.u32" } } */ +/* { dg-final { scan-assembler "(?n)mov\\.v2\\.u32.*\\{ 1, 2 \\}" } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/vec.inc b/gcc/testsuite/gcc.target/nvptx/vec.inc new file mode 100644 index 00000000000..269a9749e26 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/vec.inc @@ -0,0 +1,18 @@ +TYPE __attribute__((noinline, noclone)) +vector_load (TYPE *p) +{ + return *p; +} + +void __attribute__((noinline, noclone)) +vector_store (TYPE *p, TYPE val) +{ + *p = val; +} + +TYPE __attribute__((noinline, noclone)) +vector_const () +{ + TYPE res = {1, 2}; + return res; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c new file mode 100644 index 00000000000..e069fb49af9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_eq (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_eq (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (!compare_exponents_eq (&x, &y)) + abort (); + if (compare_exponents_eq (&x, &z)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c new file mode 100644 index 00000000000..800c32c6e07 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_eq (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_eq (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_eq (&x, &y) == 'f') + abort (); + if (compare_exponents_eq (&x, &z) == 't') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c new file mode 100644 index 00000000000..c0cedecaa7f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_gt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_gt (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_gt (&x, &y)) + abort (); + if (!compare_exponents_gt (&x, &z)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c new file mode 100644 index 00000000000..1e24355d7f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_gt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_gt (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_gt (&x, &y) == 't') + abort (); + if (compare_exponents_gt (&x, &z) == 'f') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c new file mode 100644 index 00000000000..acc24b5658e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_lt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_lt (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_lt (&x, &y)) + abort (); + if (!compare_exponents_lt (&z, &x)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c new file mode 100644 index 00000000000..b8bd278dce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_lt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_lt (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_lt (&x, &y) == 't') + abort (); + if (compare_exponents_lt (&z, &x) == 'f') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c new file mode 100644 index 00000000000..79900c21b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_unordered (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + /* This test succeeds if either exponent1 or exponent2 is NaN. */ + return scalar_cmp_exp_unordered (exponent1, exponent2); +} + +int +main () +{ + /* NaN is denoted by exponent = 2047 and fraction != 0 */ + unsigned long long int nan_image = 0x7ff0000000000003LL; + double *nan_ptr = (double *) &nan_image; + + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (!compare_exponents_unordered (&x, nan_ptr)) + abort (); + if (compare_exponents_unordered (&x, &z)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c new file mode 100644 index 00000000000..4371946a6d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_unordered (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + /* This test succeeds if either exponent1 or exponent2 is NaN. */ + if (scalar_cmp_exp_unordered (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + /* NaN is denoted by exponent = 2047 and fraction != 0 */ + unsigned long long int nan_image = 0x7ff0000000000003LL; + double *nan_ptr = (double *) &nan_image; + + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_unordered (&x, nan_ptr) == 'f') + abort (); + if (compare_exponents_unordered (&x, &z) == 't') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c new file mode 100644 index 00000000000..9e6fb085d47 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source); +} + +/* { dg-final { scan-assembler "xsxexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c new file mode 100644 index 00000000000..502241581d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_exp (source); /* { dg-error "Builtin function __builtin_vsx_scalar_extract_expq requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c new file mode 100644 index 00000000000..07e0c1de7e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source); /* { dg-error "Builtin function __builtin_vec_scalar_extract_exp not supported in this compiler configuration" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c new file mode 100644 index 00000000000..a5e31bf51ab --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned int +get_unbiased_exponent (double *p) +{ + double source = *p; + + return scalar_extract_exp (source) - 1023; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (get_unbiased_exponent (&x) != 62) + abort (); + if (get_unbiased_exponent (&z) != 49) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c new file mode 100644 index 00000000000..3920594b657 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned long long int +get_unbiased_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source) - 16383; +} + +int +main () +{ + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (get_unbiased_exponent (&x) != 126) + abort (); + if (get_unbiased_exponent (&z) != 124) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c new file mode 100644 index 00000000000..093ba337785 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_sig (source); +} + +/* { dg-final { scan-assembler "xsxsigqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c new file mode 100644 index 00000000000..0c2ec4739f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_sig (source); /* { dg-error "Builtin function __builtin_vsx_scalar_extract_sigq requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c new file mode 100644 index 00000000000..19ca4c4a09a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, producing a compiler + error because the builtin requires 64 bits. */ +#include <altivec.h> + +unsigned __int128 /* { dg-error "'__int128' is not supported on this target" } */ +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_sig (source); /* { dg-error "Builtin function __builtin_vec_scalar_extract_sig not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c new file mode 100644 index 00000000000..298268dadf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned long long int +get_significand (double *p) +{ + double source = *p; + + return scalar_extract_sig (source); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (get_significand (&x) != 0x11000000000000ULL) + abort (); + if (get_significand (&z) != 0x11010000000000ULL) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c new file mode 100644 index 00000000000..52081310ac5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_sig (source); +} + +int +main () +{ + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + /* 113 bits in the significand */ + /* our constant mantissas have 13 bits */ + + unsigned __int128 first_anticipated_result = ((__int128) 0x1100LL) << 100; + unsigned __int128 second_anticipated_result = ((__int128) 0x1101LL) << 100; + + if (get_significand (&x) != first_anticipated_result) + abort (); + if (get_significand (&z) != second_anticipated_result) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c new file mode 100644 index 00000000000..e730556c5c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return __builtin_vec_scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vsx_scalar_insert_exp_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c new file mode 100644 index 00000000000..d44e6ccec5b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vec_scalar_insert_exp not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c new file mode 100644 index 00000000000..b76c9c81145 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +double +insert_exponent (unsigned long long int *significand_p, + unsigned long long int *exponent_p) +{ + unsigned long long int significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_DOUBLE_EXP 1023 + +int +main () +{ + unsigned long long int significand_1 = 0x18000000000000LL; + unsigned long long int significand_2 = 0x1a000000000000LL; + unsigned long long int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; + unsigned long long int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; + + double x = (double) (0x1800ULL << 50); + double z = (double) (0x1a00ULL << 37); + + + if (insert_exponent (&significand_1, &exponent_1) != x) + abort (); + if (insert_exponent (&significand_2, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c new file mode 100644 index 00000000000..212563c84b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +double +insert_exponent (double *significand_p, + unsigned long long int *exponent_p) +{ + double significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_DOUBLE_EXP 1023 + +int +main () +{ + unsigned long long int significand_1 = 0x11000000000000LL; + unsigned long long int significand_2 = 0x11010000000000LL; + unsigned long long int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; + unsigned long long int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; + + double *significand_1_ptr = (double *) &significand_1; + double *significand_2_ptr = (double *) &significand_2; + + + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (insert_exponent (significand_1_ptr, &exponent_1) != x) + abort (); + if (insert_exponent (significand_2_ptr, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c new file mode 100644 index 00000000000..fc6c3817b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_QUAD_EXP 16383 + +int +main () +{ + /* most-significant bit @13, shift it to position 113 */ + unsigned __int128 significand_1 = ((__int128) 0x1100) << 100; + unsigned __int128 significand_2 = ((__int128) 0x1101) << 100; + unsigned long long int exponent_1 = 126 + BIAS_FOR_QUAD_EXP; + unsigned long long int exponent_2 = 124 + BIAS_FOR_QUAD_EXP; + + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (insert_exponent (&significand_1, &exponent_1) != x) + abort (); + if (insert_exponent (&significand_2, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c new file mode 100644 index 00000000000..5843880d382 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_QUAD_EXP 16383 + +int +main () +{ + /* most-significant bit @13, shift it to position 113 */ + unsigned __int128 significand_1 = ((unsigned __int128) 0x1100) << 100; + unsigned __int128 significand_2 = ((unsigned __int128) 0x1101) << 100; + unsigned long long int exponent_1 = 126 + BIAS_FOR_QUAD_EXP; + unsigned long long int exponent_2 = 124 + BIAS_FOR_QUAD_EXP; + + __ieee128 *significand_1_ptr = (__ieee128 *) &significand_1; + __ieee128 *significand_2_ptr = (__ieee128 *) &significand_2; + + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (insert_exponent (significand_1_ptr, &exponent_1) != x) + abort (); + if (insert_exponent (significand_2_ptr, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c new file mode 100644 index 00000000000..d896fa5d7b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +/* { dg-final { scan-assembler "xsiexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c new file mode 100644 index 00000000000..fe565c8f416 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return __builtin_vec_scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vsx_scalar_insert_exp_q requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c new file mode 100644 index 00000000000..3a3f1c4aa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, /* { dg-error "'__int128' is not supported on this target" } */ + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; /* { dg-error "'__int128' is not supported on this target" } */ + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vec_scalar_insert_exp not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c new file mode 100644 index 00000000000..dca5c0ab5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +/* { dg-final { scan-assembler "xsiexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c new file mode 100644 index 00000000000..32fd8b1deee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p, const int condition_flag) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, condition_flag); /* { dg-error "argument 2 must be a 7-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c new file mode 100644 index 00000000000..0065b77746a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_test_data_class (source, 3); /* { dg-error "Builtin function __builtin_vsx_scalar_test_data_class_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c new file mode 100644 index 00000000000..46c4fd22735 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c @@ -0,0 +1,44 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_denormal (double *p) +{ + double source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 3); +} + +int +main () +{ + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + double denormal_plus = scalar_insert_exp (0x0008000000000000ULL, 0x0ULL); + double denormal_minus = scalar_insert_exp (0x8008000000000000ULL, 0x0ULL); + double not_denormal = scalar_insert_exp (0x8000000000000000ULL, 1023ULL); + + if (!test_denormal (&denormal_plus)) + abort (); + if (!test_denormal (&denormal_minus)) + abort (); + if (test_denormal (¬_denormal)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c new file mode 100644 index 00000000000..0beb66ae643 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_zero (float *p) +{ + float source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 12); +} + +int +main () +{ + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + unsigned int zero_plus_image = 0x0; + unsigned int zero_minus_image = 0x80000000; + unsigned int non_zero_image = 0x60000000; + + float *zero_plus_p = (float *) &zero_plus_image; + float *zero_minus_p = (float *) &zero_minus_image; + float *not_zero_p = (float *) &non_zero_image; + + if (!test_zero (zero_plus_p)) + abort (); + if (!test_zero (zero_minus_p)) + abort (); + if (test_zero (not_zero_p)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c new file mode 100644 index 00000000000..90dd64637c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c @@ -0,0 +1,54 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_nan (__ieee128 *p) +{ + __ieee128 source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 0x40); +} + +int +main () +{ + /* NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN is a + * Signaling NaN. Otherwise, it is a Quiet NaN. */ + __int128 signal_significand = (__int128) 0xffffffff; + __int128 quiet_significand = (((__int128) 0x1) << 112) | 0xffffffff; + __int128 a_number_significand = (((__int128) 0x1) << 112); + unsigned long long int nan_exponent = 0x7fff; + unsigned long long int a_number_exponent = 16383; + + __ieee128 signaling_nan = + scalar_insert_exp (signal_significand, nan_exponent); + __ieee128 quiet_nan = + scalar_insert_exp (quiet_significand, nan_exponent); + __ieee128 a_number = + scalar_insert_exp (a_number_significand, a_number_exponent); + + if (!test_nan (&signaling_nan)) + abort (); + if (!test_nan (&quiet_nan)) + abort (); + if (test_nan (&a_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c new file mode 100644 index 00000000000..5da7a3fe1b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c @@ -0,0 +1,56 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_infinity (__ieee128 *p) +{ + __ieee128 source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 0x30); +} + +int +main () +{ + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * 32767 in ieee128 format + * and a zero fraction value. */ + __int128 plus_significand = (__int128) 0; + __int128 minus_significand = ((__int128) 0x1) << 127; + __int128 a_number_significand = (((__int128) 0x1) << 112); + + unsigned long long int infinite_exponent = 0x7fff; + unsigned long long int a_number_exponent = 16383; + + __ieee128 plus_infinity = + scalar_insert_exp (plus_significand, infinite_exponent); + __ieee128 minus_infinity = + scalar_insert_exp (minus_significand, infinite_exponent); + __ieee128 a_number = + scalar_insert_exp (a_number_significand, a_number_exponent); + + if (!test_infinity (&plus_infinity)) + abort (); + if (!test_infinity (&minus_infinity)) + abort (); + if (test_infinity (&a_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c new file mode 100644 index 00000000000..25192506992 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, 3); +} + +/* { dg-final { scan-assembler "xststdcqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c new file mode 100644 index 00000000000..28c1e090ce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, 256); /* { dg-error "argument 2 must be a 7-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c new file mode 100644 index 00000000000..13fee32cdf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_neg (source); +} + +/* { dg-final { scan-assembler "xststdcqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c new file mode 100644 index 00000000000..041a4a1c820 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_test_neg_qp (source); /* { dg-error "Builtin function __builtin_vsx_scalar_test_neg_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c new file mode 100644 index 00000000000..497ac7b14aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (double *p) +{ + double source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + double neg_number = (double) -1; + double plus_number = (double) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c new file mode 100644 index 00000000000..f7dfb5f9ed6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (float *p) +{ + float source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + float neg_number = (float) -1; + float plus_number = (float) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c new file mode 100644 index 00000000000..fff837ace70 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + __ieee128 neg_number = (__ieee128) -1; + __ieee128 plus_number = (__ieee128) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c new file mode 100644 index 00000000000..ab0e05e17c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned int +get_exponents (__vector float *p) +{ + __vector float source = *p; + + return vec_extract_exp (source); +} + +unsigned int bias_float_exp (int unbiased_exp) +{ + return (unsigned int) (unbiased_exp + 127); +} + +int +main () +{ + __vector float argument; + __vector unsigned int result; + + argument[0] = (float) (0x1 << 10); + argument[1] = (float) (0x1 << 9); + argument[2] = (float) (0x1 << 8); + argument[3] = (float) (0x1 << 7); + + result = get_exponents (&argument); + if ((result[0] != bias_float_exp (10)) || + (result[1] != bias_float_exp (9)) || + (result[2] != bias_float_exp (8)) || (result[3] != bias_float_exp (7))) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c new file mode 100644 index 00000000000..1dabd6cf2c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned long long int +get_exponents (__vector double *p) +{ + __vector double source = *p; + + return vec_extract_exp (source); +} + +unsigned long long int +bias_double_exp (long long int unbiased_exp) +{ + return (unsigned long long int) (unbiased_exp + 1023); +} + +int +main () +{ + __vector double argument; + __vector unsigned long long int result; + + argument[0] = (double) (0x1 << 22); + argument[1] = (double) (0x1 << 23); + + result = get_exponents (&argument); + if ((result[0] != bias_double_exp (22)) || + (result[1] != bias_double_exp (23))) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c new file mode 100644 index 00000000000..6d4a9277f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned int +get_significands (__vector float *p) +{ + __vector float source = *p; + + return vec_extract_sig (source); +} + +int +main () +{ + __vector float argument; + __vector unsigned int result; + + argument[0] = (float) (0x1234 << 10); + argument[1] = (float) (0x4321 << 9); + argument[2] = (float) (0xbabe << 8); + argument[3] = (float) (0xcafe << 7); + + result = get_significands (&argument); + if ((result[0] != 0x91a000) || (result[1] != 0x864200) || + (result[2] != 0xbabe00) || (result[3] != 0xcafe00)) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c new file mode 100644 index 00000000000..ff2ca48798f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned long long int +get_significands (__vector double *p) +{ + __vector double source = *p; + + return vec_extract_sig (source); +} + +int +main () +{ + __vector double argument; + __vector unsigned long long int result; + + argument[0] = (double) (0xbabeLL << 22); + argument[1] = (double) (0xcafeLL << 23); + + result = get_significands (&argument); + if ((result[0] != (0xbabeULL << 37)) || (result[1] != (0xcafeULL << 37))) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c new file mode 100644 index 00000000000..020d09abe13 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c @@ -0,0 +1,44 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector float +make_floats (__vector float *significands_p, + __vector unsigned int *exponents_p) +{ + __vector float significands = *significands_p; + __vector unsigned int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned int significands; + __vector float *significands_p = (__vector float *) &significands; + __vector unsigned int exponents; + __vector float result; + + /* 24 bits in significand, plus the sign bit: 0x80ffffff */ + significands[0] = 0x00800000; /* 1.0 */ + significands[1] = 0x00c00000; /* 1.5 */ + significands[2] = 0x80e00000; /* -1.75 */ + significands[3] = 0x80c00000; /* -1.5 */ + + exponents[0] = 127; /* exp = 0: 1.0 */ + exponents[1] = 128; /* exp = 1: 3.0 */ + exponents[2] = 129; /* exp = 2: -7.0 */ + exponents[3] = 125; /* exp = -2: -0.375 */ + + result = make_floats (significands_p, &exponents); + if ((result[0] != 1.0f) || + (result[1] != 3.0f) || (result[2] != -7.0f) || (result[3] != -0.375f)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c new file mode 100644 index 00000000000..5bf2c9cfdaa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector double +make_doubles (__vector double *significands_p, + __vector unsigned long long int *exponents_p) +{ + __vector double significands = *significands_p; + __vector unsigned long long int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned long long int significands; + __vector double *significands_p = (__vector double *) &significands; + __vector unsigned long long int exponents; + __vector double result; + + /* 53 bits in significand, plus the sign bit: 0x8000_0000_0000_0000 */ + significands[0] = 0x0010000000000000; /* 1.0 */ + significands[1] = 0x801c000000000000; /* -1.75 */ + + exponents[0] = 1023; /* exp = 0: 1.0 */ + exponents[1] = 1021; /* exp = -2: -0.4375 (7/16) */ + + result = make_doubles (significands_p, &exponents); + if ((result[0] != 1.0) || (result[1] != -0.4375)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c new file mode 100644 index 00000000000..3f9bd988aad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector float +make_floats (__vector unsigned int *significands_p, + __vector unsigned int *exponents_p) +{ + __vector unsigned int significands = *significands_p; + __vector unsigned int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned int significands; + __vector unsigned int exponents; + __vector float result; + + /* 24 bits in significand, plus the sign bit: 0x80ffffff */ + significands[0] = 0x00800000; /* 1.0 */ + significands[1] = 0x00c00000; /* 1.5 */ + significands[2] = 0x80e00000; /* -1.75 */ + significands[3] = 0x80c00000; /* -1.5 */ + + exponents[0] = 127; /* exp = 0: 1.0 */ + exponents[1] = 128; /* exp = 1: 3.0.0 */ + exponents[2] = 129; /* exp = 2: -7.0 */ + exponents[3] = 125; /* exp = -2: -0.375 */ + + result = make_floats (&significands, &exponents); + if ((result[0] != 1.0f) || + (result[1] != 3.0f) || (result[2] != -7.0f) || (result[3] != -0.375f)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c new file mode 100644 index 00000000000..5dc71951aee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector double +make_doubles (__vector unsigned long long int *significands_p, + __vector unsigned long long int *exponents_p) +{ + __vector unsigned long long int significands = *significands_p; + __vector unsigned long long int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned long long int significands; + __vector unsigned long long int exponents; + __vector double result; + + /* 53 bits in significand, plus the sign bit: 0x8000_0000_0000_0000 */ + significands[0] = 0x0010000000000000; /* 1.0 */ + significands[1] = 0x801c000000000000; /* -1.75 */ + + exponents[0] = 1023; /* exp = 0: 1.0 */ + exponents[1] = 1021; /* exp = -2: -0.4375 (7/16) */ + + result = make_doubles (&significands, &exponents); + if ((result[0] != 1.0) || (result[1] != -0.4375)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c new file mode 100644 index 00000000000..636a3012612 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c @@ -0,0 +1,112 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +/* Flags to select tests: + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal */ + +__vector bool int +test_nan (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x40); +} + +__vector bool int +test_infinity (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x30); +} + +__vector bool int +test_zero (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x0c); +} + +__vector bool int +test_denormal (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x03); +} + +float +float_scalar_insert_exp (unsigned int significand, unsigned int exponent) +{ + float result; + unsigned int *result_as_uip = (unsigned int *) &result; + + *result_as_uip = (significand & ~0x800000) | ((exponent & 0xff) << 23); + return result; +} + +int +main () +{ + __vector float argument; + __vector bool result; + + unsigned int signaling_significand = 0x00a00000; + unsigned int quiet_significand = 0x00c00000; + unsigned int one_significand = 0x00800000; + unsigned int three_significand = 0x00c00000; + unsigned int five_significand = 0x00a00000; + unsigned int zero_significand = 0x00000000; + unsigned int minus_zero_significand = 0x80000000; + + /* A NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN + * is a Signaling NaN. Otherwise, it is a Quiet NaN. */ + argument[0] = float_scalar_insert_exp (signaling_significand, 255); + argument[1] = float_scalar_insert_exp (quiet_significand, 255); + argument[2] = 1.0f; + argument[3] = -0.07f; + result = test_nan (&argument); + if (!result[0] || !result[1] || result[2] || result[3]) + abort (); + + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * and a zero fraction value. The difference between +infinity and + * -infinity is the value of the sign bit. */ + argument[2] = float_scalar_insert_exp (zero_significand, 255); + argument[3] = float_scalar_insert_exp (minus_zero_significand, 255); + result = test_infinity (&argument); + if (result[0] || result[1] || !result[2] || !result[3]) + abort (); + + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + argument[1] = float_scalar_insert_exp (minus_zero_significand, 0); + argument[2] = float_scalar_insert_exp (zero_significand, 0); + result = test_zero (&argument); + if (result[0] || !result[1] || !result[2] || result[3]) + abort (); + + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + argument[0] = float_scalar_insert_exp (five_significand, 0); + argument[3] = float_scalar_insert_exp (three_significand, 0); + result = test_denormal (&argument); + if (!result[0] || result[1] || result[2] || !result[3]) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c new file mode 100644 index 00000000000..5ccac12df87 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c @@ -0,0 +1,125 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +/* Flags to select tests: + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal */ + +__vector bool long long int +test_nan (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x40); +} + +__vector bool long long int +test_infinity (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x30); +} + +__vector bool long long int +test_zero (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x0c); +} + +__vector bool long long int +test_denormal (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x03); +} + +int +main () +{ + __vector double special_argument; + __vector double nonspecial_argument; + __vector bool long long int result; + + unsigned long long int signaling_significand = + 0x0017000000000000ULL; + unsigned long long int quiet_significand = + 0x001f000000000000ULL; + unsigned long long int one_significand = + 0x0010000000000000ULL; + unsigned long long int three_significand = + 0x0018000000000000ULL; + unsigned long long int five_significand = + 0x0014000000000000ULL; + unsigned long long int zero_significand = + 0x0000000000000000ULL; + unsigned long long int minus_zero_significand = + 0x8000000000000000ULL; + + nonspecial_argument[0] = -3.825; + nonspecial_argument[1] = 3.14159; + + /* A NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN + * is a Signaling NaN. Otherwise, it is a Quiet NaN. */ + special_argument[0] = scalar_insert_exp (signaling_significand, 2047); + special_argument[1] = scalar_insert_exp (quiet_significand, 2047); + result = test_nan (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_nan (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * and a zero fraction value. The difference between +infinity and + * -infinity is the value of the sign bit. */ + special_argument[0] = scalar_insert_exp (zero_significand, 2047); + special_argument[1] = scalar_insert_exp (minus_zero_significand, 2047); + result = test_infinity (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_infinity (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + special_argument[0] = scalar_insert_exp (minus_zero_significand, 0); + special_argument[1] = scalar_insert_exp (zero_significand, 0); + result = test_zero (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_zero (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + special_argument[0] = scalar_insert_exp (five_significand, 0); + special_argument[1] = scalar_insert_exp (three_significand, 0); + result = test_denormal (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_denormal (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c index 8d8d643e088..3702bdd77fe 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c index a4260b51b79..a6f5d5084c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c index f532c6a3bb5..45e5bdd8510 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c index b3515259fca..52f78df1267 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c index 8701d9fbd1d..3ca56665033 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c index 2835adedced..e43e2da422a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c index 418d336b43e..345a7eb9def 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c index 1d51b5a75bb..f2e1a58f5ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c index df34d53ab86..481b09f77ce 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c index e5fe12d4ee0..3ba7e97dd47 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c index 645e00f05ee..c383b7914e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c index f290b838001..61d962b9150 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-check.h b/gcc/testsuite/gcc.target/powerpc/bmi-check.h index 35a2ac29bc3..1a9ad13f38c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-check.h +++ b/gcc/testsuite/gcc.target/powerpc/bmi-check.h @@ -13,6 +13,7 @@ do_test (void) int main () { +#ifdef __BUILTIN_CPU_SUPPORTS__ /* Need 64-bit for 64-bit longs as single instruction. */ if ( __builtin_cpu_supports ("ppc64") ) { @@ -25,6 +26,6 @@ main () else printf ("SKIPPED\n"); #endif - +#endif /* __BUILTIN_CPU_SUPPORTS__ */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c index 25b096ad0bc..25ba3dc238e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c index 75397e53eb6..1b80ccbdaa9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c index b2a6d4d74ea..f0943d7f974 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c index a09d5d24b51..33f1748b44e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-check.h b/gcc/testsuite/gcc.target/powerpc/bmi2-check.h index fa7d4c02a45..ab032eaa7ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-check.h +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-check.h @@ -13,6 +13,7 @@ do_test (void) int main () { +#ifdef __BUILTIN_CPU_SUPPORTS__ /* The BMI2 test for pext test requires the Bit Permute doubleword (bpermd) instruction added in PowerISA 2.06 along with the VSX facility. So we can test for arch_2_06. */ @@ -27,7 +28,7 @@ main () else printf ("SKIPPED\n"); #endif - +#endif /* __BUILTIN_CPU_SUPPORTS__ */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c index eda74690589..870679c779f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include "bmi2-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c index a6fc38cbf55..b8327741c3a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c index 5334de20fc5..b1e4a13c2af 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include "bmi2-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c index ff119262c64..d57f05503c5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c index 12cf92eec2c..a07567389d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c index 01e1fdaf538..1268239e61f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c index 9450ef56aed..762ed1b0325 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c index b76ae81b5bc..5e269ec47de 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c new file mode 100644 index 00000000000..acaebb60f1c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +#include <altivec.h> + +void abort (void); + +int main() { + int i; + vector float vfa, vfb; + vector unsigned short vur, vuexpt; + + vfa = (vector float){3.4, 5.0, 20.0, 50.9 }; + vfb = (vector float){10.0, 40.0, 70.0, 100.0 }; + vuexpt = (vector unsigned short){ 3, 5, 20, 50, + 10, 40, 70, 100}; + + vur = vec_pack_to_short_fp32 (vfa, vfb); + + for(i = 0; i< 8; i++) { + if (vur[i] != vuexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c new file mode 100644 index 00000000000..2f317077fcb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c @@ -0,0 +1,72 @@ +/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + vector int vsia; + vector unsigned int vsir, vsiexpt; + vector unsigned int vuia, vuir, vuiexpt; + vector signed long long vslla; + vector unsigned long long vsllr, vsllexpt; + vector unsigned long long vulla, vullr, vullexpt; + vector __int128_t vs128a; + vector __uint128_t vs128r, vs128expt; + vector __uint128_t vu128a, vu128r, vu128expt; + + /* Returns a vector with each element containing the parity of the low-order + bit of each of the bytes in that element. Note results are always + returned in an unsinged type, per the ABI spec. */ + vsia = (vector int) {0x10101010, 0x10101011, 0x10101111, 0x10111111}; + vsiexpt = (vector unsigned int){0x0, 0x1, 0x0, 0x1}; + + vuia = (vector unsigned int) {0x000010000, 0x00010001, + 0x10100000, 0x000010101}; + vuiexpt = (vector unsigned int){0x1, 0x0, 0x0, 0x1}; + + vslla = (vector long long) {0x0000000000010000, 0x0001000100010000}; + vsllexpt = (vector unsigned long long){0x1, 0x1}; + + vulla = (vector unsigned long long) {0x0000000000000001, + 0x0001000000000001}; + vullexpt = (vector unsigned long long){0x1, 0x0}; + + vs128a = (vector __int128_t) {0x0000000000001}; + vs128expt = (vector __uint128_t) {0x1}; + vu128a = (vector __uint128_t) {0x1000000000001}; + vu128expt = (vector __uint128_t) {0x0}; + + vsir = vec_parity_lsbb(vsia); + vuir = vec_parity_lsbb(vuia); + vsllr = vec_parity_lsbb(vslla); + vullr = vec_parity_lsbb(vulla); + vs128r = vec_parity_lsbb(vs128a); + vu128r = vec_parity_lsbb(vu128a); + + for(i = 0; i< 4; i++) { + if (vsir[i] != vsiexpt[i]) + abort(); + + if (vuir[i] != vuiexpt[i]) + abort(); + } + + for(i = 0; i< 2; i++) { + if (vsllr[i] != vsllexpt[i]) + abort(); + + if (vullr[i] != vullexpt[i]) + abort(); + } + + if (vs128r[0] != vs128expt[0]) + abort(); + + if (vu128r[0] != vu128expt[0]) + abort(); +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c new file mode 100644 index 00000000000..24589b55639 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + vector float vfr, vfexpt; + vector unsigned short vusha; + + /* 1.0, -2.0, 0.0, 8.5, 1.5, 0.5, 1.25, -0.25 */ + vusha = (vector unsigned short){0B011110000000000, 0B1100000000000000, + 0B000000000000000, 0B0100100001000000, + 0B011111000000000, 0B0011100000000000, + 0B011110100000000, 0B1011010000000000}; + + vfexpt = (vector float){1.0, -2.0, 0.0, 8.5}; + vfr = vec_extract_fp_from_shorth(vusha); + + for (i=0; i<4; i++) { + if (vfr[i] != vfexpt[i]) + abort(); + } + + vfexpt = (vector float){1.5, 0.5, 1.25, -0.25}; + vfr = vec_extract_fp_from_shortl(vusha); + + for (i=0; i<4; i++) { + if (vfr[i] != vfexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c index 08b7a5395d2..17bb9b3225b 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c @@ -5,53 +5,181 @@ #include <altivec.h> // vector +#ifdef DEBUG +#include <stdio.h> +#endif + #define ALL 1 #define EVEN 2 #define ODD 3 void abort (void); -void test_result_sp(int check, vector float vec_result, vector float vec_expected) +void test_int_result(int check, vector int vec_result, vector int vec_expected) { int i; - for(i = 0; i<4; i++) { - switch (check) { - case ALL: - break; - case EVEN: - if (i%2 == 0) + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: break; - else - continue; - case ODD: - if (i%2 != 0) + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} + +void test_unsigned_int_result(int check, vector unsigned int vec_result, + vector unsigned int vec_expected) +{ + int i; + + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: break; - else - continue; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_unsigned int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} - if (vec_result[i] != vec_expected[i]) - abort(); +void test_ll_int_result(vector long long int vec_result, + vector long long int vec_expected) +{ + int i; + + for (i = 0; i < 2; i++) + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_ll_int_result: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } +} + +void test_ll_unsigned_int_result(vector long long unsigned int vec_result, + vector long long unsigned int vec_expected) +{ + int i; + + for (i = 0; i < 2; i++) + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_ll_unsigned_int_result: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } +} + +void test_result_sp(int check, vector float vec_result, + vector float vec_expected) +{ + int i; + for(i = 0; i<4; i++) { + + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_result_sp: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } } } void test_result_dp(vector double vec_result, vector double vec_expected) { - if (vec_result[0] != vec_expected[0]) + if (vec_result[0] != vec_expected[0]) { +#ifdef DEBUG + printf("Test_result_dp: "); + printf("vec_result[0] (%lld) != vec_expected[0] (%lld)\n", + vec_result[0], vec_expected[0]); +#else abort(); +#endif + } - if (vec_result[1] != vec_expected[1]) + if (vec_result[1] != vec_expected[1]) { +#ifdef DEBUG + printf("Test_result_dp: "); + printf("vec_result[1] (%lld) != vec_expected[1] (%lld)\n", + vec_result[1], vec_expected[1]); +#else abort(); +#endif + } } int main() { int i; - vector unsigned int vec_unint; - vector signed int vec_int; + vector unsigned int vec_unint, vec_uns_int_expected, vec_uns_int_result; + vector signed int vec_int, vec_int_expected, vec_int_result; vector long long int vec_ll_int0, vec_ll_int1; + vector long long int vec_ll_int_expected, vec_ll_int_result; vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1; + vector long long unsigned int vec_ll_uns_int_expected, vec_ll_uns_int_result; vector float vec_flt, vec_flt_result, vec_flt_expected; vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected; @@ -163,4 +291,67 @@ int main() vec_flt_expected = (vector float){0.00, 34.00, 0.00, 97.00}; vec_flt_result = vec_floato (vec_dble0); test_result_sp(ODD, vec_flt_result, vec_flt_expected); + + /* Convert single precision float to int */ + vec_flt = (vector float){-14.30, 34.00, 22.00, 97.00}; + vec_int_expected = (vector signed int){-14, 34, 22, 97}; + vec_int_result = vec_signed (vec_flt); + test_int_result (ALL, vec_int_result, vec_int_expected); + + /* Convert double precision float to long long int */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_ll_int_expected = (vector long long signed int){-124, 81234}; + vec_ll_int_result = vec_signed (vec_dble0); + test_ll_int_result (vec_ll_int_result, vec_ll_int_expected); + + /* Convert two double precision vector float to vector int */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_dble1 = (vector double){-24.370, 8354.99}; + vec_int_expected = (vector signed int){-124, 81234, -24, 8354}; + vec_int_result = vec_signed2 (vec_dble0, vec_dble1); + test_int_result (ALL, vec_int_result, vec_int_expected); + + /* Convert double precision vector float to vector int, even words */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_int_expected = (vector signed int){-124, 0, 81234, 0}; + vec_int_result = vec_signede (vec_dble0); + test_int_result (EVEN, vec_int_result, vec_int_expected); + + /* Convert double precision vector float to vector int, odd words */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_int_expected = (vector signed int){0, -124, 0, 81234}; + vec_int_result = vec_signedo (vec_dble0); + test_int_result (ODD, vec_int_result, vec_int_expected); + + /* Convert double precision float to long long unsigned int */ + vec_dble0 = (vector double){124.930, 8134.49}; + vec_ll_uns_int_expected = (vector long long unsigned int){124, 8134}; + vec_ll_uns_int_result = vec_unsigned (vec_dble0); + test_ll_unsigned_int_result (vec_ll_uns_int_result, + vec_ll_uns_int_expected); + + /* Convert two double precision vector float to vector unsigned int */ + vec_dble0 = (vector double){124.930, 8134.49}; + vec_dble1 = (vector double){24.370, 834.99}; + vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834}; + vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1); + test_unsigned_int_result (ALL, vec_uns_int_result, + vec_uns_int_expected); + + /* Convert double precision vector float to vector unsigned int, + even words */ + vec_dble0 = (vector double){3124.930, 8234.49}; + vec_uns_int_expected = (vector unsigned int){3124, 0, 8234, 0}; + vec_uns_int_result = vec_unsignede (vec_dble0); + test_unsigned_int_result (EVEN, vec_uns_int_result, + vec_uns_int_expected); + + /* Convert double precision vector float to vector unsigned int, + odd words */ + vec_dble0 = (vector double){1924.930, 81234.49}; + vec_uns_int_expected = (vector unsigned int){0, 1924, 0, 81234}; + vec_uns_int_result = vec_unsignedo (vec_dble0); + test_unsigned_int_result (ODD, vec_uns_int_result, + vec_uns_int_expected); } + diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c new file mode 100644 index 00000000000..f7c3c3d9138 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c @@ -0,0 +1,393 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O2 -mvsx -mcpu=power7" } */ + +#include <altivec.h> // vector + +#ifdef DEBUG +#include <stdio.h> +#endif + +#define VBC 0 +#define VSC 1 +#define VUC 2 +#define VBS 3 +#define VSS 4 +#define VUS 5 +#define VBI 6 +#define VI 7 +#define VUI 8 +#define VLLB 9 +#define VLLI 10 +#define VLLUI 11 +#define VF 12 +#define VD 13 + +union vector_value +{ + vector bool char vbc; + vector signed char vsc; + vector unsigned char vuc; + vector bool short vbs; + vector signed short vss; + vector unsigned short vus; + vector bool int vbi; + vector signed int vi; + vector unsigned int vui; + vector bool long long vllb; + vector long long signed int vlli; + vector long long unsigned int vllui; + vector float vf; + vector double vd; +} vec_element; + +struct vector_struct +{ + int vector_id; + int element_size; // element size in bytes + union vector_value vec; +} vec; + +void abort (void); + +void test_results(struct vector_struct *vec_result, + struct vector_struct *vec_expected) +{ + int i; + int num_elements; + if (vec_result->element_size != vec_expected->element_size) +#ifdef DEBUG + printf("vec_result->element_size != vec_expected->element_size\n"); +#else + abort(); +#endif + + if (vec_result->vector_id != vec_expected->vector_id) +#ifdef DEBUG + printf("vec_result->vector_id != vec_expected->vector_id\n"); +#else + abort(); +#endif + + num_elements = 16 / vec_result->element_size; + + for (i = 0; i<num_elements; i++) { + switch (vec_result->vector_id) { + case VBC: + if (vec_result->vec.vbc[i] != vec_expected->vec.vbc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbc[%d] (%d) != ", + i, vec_result->vec.vbc[i]); + printf("vec_expected->vec.vbc[%d] (%d)\n", + i, vec_expected->vec.vbc[i]); +#else + abort(); +#endif + } + break; + + case VSC: + if (vec_result->vec.vsc[i] != vec_expected->vec.vsc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vsc[%d] (%d) != ", + i, vec_result->vec.vsc[i]); + printf("vec_expected->vec.vsc[%d] (%d)\n", + i, vec_expected->vec.vsc[i]); +#else + abort(); +#endif + } + break; + + case VUC: + if (vec_result->vec.vuc[i] != vec_expected->vec.vuc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vuc[%d] (%d) != ", + i, vec_result->vec.vuc[i]); + printf("vec_expected->vec.vuc[%d] (%d)\n", + i, vec_expected->vec.vuc[i]); +#else + abort(); +#endif + } + break; + + case VBS: + if (vec_result->vec.vbs[i] != vec_expected->vec.vbs[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbs[%d] (%d) != ", + i, vec_result->vec.vbs[i]); + printf("vec_expected->vec.vbs[%d] (%d)\n", + i, vec_expected->vec.vbs[i]); +#else + abort(); +#endif + } + break; + + case VSS: + if (vec_result->vec.vss[i] != vec_expected->vec.vss[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vss[%d] (%d) != ", + i, vec_result->vec.vss[i]); + printf("vec_expected->vec.vss[%d] (%d)\n", + i, vec_expected->vec.vss[i]); +#else + abort(); +#endif + } + break; + + case VUS: + if (vec_result->vec.vus[i] != vec_expected->vec.vus[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vus[%d] (%d) != ", + i, vec_expected->vec.vus[i]); + printf("vec_expected->vec.vus[%d] (%d)\n", + i, vec_expected->vec.vus[i]); +#else + abort(); +#endif + } + break; + + case VBI: + if (vec_result->vec.vbi[i] != vec_expected->vec.vbi[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbi[%d] (%d) != ", + i, vec_result->vec.vbi[i]); + printf("vec_expected->vec.vbi[%d] (%d)\n", + i, vec_expected->vec.vbi[i]); +#else + abort(); +#endif + } + break; + + case VI: + if (vec_result->vec.vi[i] != vec_expected->vec.vi[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vi[%d] (%d) != ", + i, vec_result->vec.vi[i]); + printf("vec_expected->vec.vi[%d] (%d)\n", + i, vec_expected->vec.vi[i]); +#else + abort(); +#endif + } + break; + + case VUI: + if (vec_result->vec.vui[i] != vec_expected->vec.vui[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vui[%d] (%u) != ", + i, vec_result->vec.vui[i]); + printf("vec_expected->vec.vui[%u] (%d)\n", + i, vec_expected->vec.vui[i]); +#else + abort(); +#endif + } + break; + + case VLLB: + if (vec_result->vec.vllb[i] != vec_expected->vec.vllb[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vllb[%d] (%lld != ", + i, vec_result->vec.vllb[i]); + printf("vec_expected->vec.vllb[%lld] (%d)\n", + i, vec_expected->vec.vllb[i]); +#else + abort(); +#endif + } + break; + + case VLLI: + if (vec_result->vec.vlli[i] != vec_expected->vec.vlli[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vlli[%d] (%d) != ", + i, vec_result->vec.vlli[i]); + printf("vec_expected->vec.vlli[%d] (%d)\n", + i, vec_expected->vec.vlli[i]); +#else + abort(); +#endif + } + break; + + case VLLUI: + if (vec_result->vec.vllui[i] != vec_expected->vec.vllui[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vllui[%d] (%llu) != ", + i, vec_result->vec.vllui[i]); + printf("vec_expected->vec.vllui[%d] (%llu)\n", + i, vec_expected->vec.vllui[i]); +#else + abort(); +#endif + } + break; + + case VF: + if (vec_result->vec.vf[i] != vec_expected->vec.vf[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vf[%d] (%f) != ", + i, vec_result->vec.vf[i]); + printf("vec_expected->vec.vf[%d] (%f)\n", + i, vec_expected->vec.vf[i]); +#else + abort(); +#endif + } + break; + + case VD: + if (vec_result->vec.vd[i] != vec_expected->vec.vd[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vd[%d] (%f) != ", + i, vec_result->vec.vd[i]); + printf("vec_expected->vec.vd[%d] (%f)\n", + i, vec_expected->vec.vd[i]); +#else + abort(); +#endif + } + break; + + default: +#ifdef DEBUG + printf("Unknown case.\n"); +#else + abort(); +#endif + } + } +} + +int main() +{ + int i; + struct vector_struct vec_src, vec_expected, vec_result; + + vec_src.vec.vbc = (vector bool char){ 0, 1, 0, 0, 1, 1, 0, 0, + 0, 1, 1, 1, 0, 0, 0, 0 }; + vec_expected.vec.vbc = (vector bool char){ 0, 0, 0, 0, 1, 1, 1, 0, + 0, 0, 1, 1, 0, 0, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VBC; + vec_result.vec.vbc = vec_reve (vec_src.vec.vbc); + test_results(&vec_result, &vec_expected); + + vec_src.vec.vsc = (vector signed char){ 0, 1, -2, -3, 4, 5, -6, -7, 8, + 9, -10, -11, 12, 13, -14, -15 }; + vec_expected.vec.vsc = (vector signed char){ -15, -14, 13, 12, -11, -10, + 9, 8, -7, -6, 5, 4, -3, -2, + 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VSC; + vec_result.vec.vsc = vec_reve (vec_src.vec.vsc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vuc = (vector unsigned char){ 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25 }; + vec_expected.vec.vuc = (vector unsigned char){ 25, 24, 23, 22, 21, 20, + 19, 18, 17, 16, 15, 14, 13, + 12, 11, 10 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VUC; + vec_result.vec.vuc = vec_reve (vec_src.vec.vuc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbs = (vector bool short){ 0, 0, 1, 1, 0, 1, 0, 1 }; + vec_expected.vec.vbs = (vector bool short){ 1, 0, 1, 0, 1, 1, 0, 0 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VBS; + vec_result.vec.vbs = vec_reve (vec_src.vec.vbs); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vss = (vector signed short){ -1, -2, 3, 4, -5, -6, 7, 8 }; + vec_expected.vec.vss = (vector signed short){ 8, 7, -6, -5, 4, 3, -2, -1 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VSS; + vec_result.vec.vss = vec_reve (vec_src.vec.vss); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vus = (vector unsigned short){ 11, 22, 33, 44, 55, 66, 77, 88 }; + vec_expected.vec.vus = (vector unsigned short){ 88, 77, 66, 55, + 44, 33, 22, 11 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VUS; + vec_result.vec.vus = vec_reve (vec_src.vec.vus); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbi = (vector bool int){ 0, 1, 1, 1 }; + vec_expected.vec.vbi = (vector bool int){ 1, 1, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VBI; + vec_result.vec.vbi = vec_reve (vec_src.vec.vbi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vi = (vector signed int){ -1, 3, -5, 1234567 }; + vec_expected.vec.vi = (vector signed int){1234567, -5, 3, -1}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VI; + vec_result.vec.vi = vec_reve (vec_src.vec.vi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vui = (vector unsigned int){ 9, 11, 15, 2468013579 }; + vec_expected.vec.vui = (vector unsigned int){2468013579, 15, 11, 9}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VUI; + vec_result.vec.vui = vec_reve (vec_src.vec.vui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllb = (vector bool long long ){ 0, 1 }; + vec_expected.vec.vllb = (vector bool long long){1, 0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLB; + vec_result.vec.vllb = vec_reve (vec_src.vec.vllb); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vlli = (vector long long int){ -12, -12345678901234 }; + vec_expected.vec.vlli = (vector long long int){-12345678901234, -12}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLI; + vec_result.vec.vlli = vec_reve (vec_src.vec.vlli); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllui = (vector unsigned long long int){ 102, 9753108642 }; + vec_expected.vec.vllui = (vector unsigned long long int){9753108642, 102}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLUI; + vec_result.vec.vllui = vec_reve (vec_src.vec.vllui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vf = (vector float){ -21., 3.5, -53., 78. }; + vec_expected.vec.vf = (vector float){78., -53, 3.5, -21}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VF; + vec_result.vec.vf = vec_reve (vec_src.vec.vf); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vd = (vector double){ 34.0, 97.0 }; + vec_expected.vec.vd = (vector double){97.0, 34.0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VD; + vec_result.vec.vd = vec_reve (vec_src.vec.vd); + test_results (&vec_result, &vec_expected); +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c new file mode 100644 index 00000000000..8e8fcabbe82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c @@ -0,0 +1,95 @@ +/* { dg-do run { target { powerpc*-*-* && { p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 " } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + + vector signed char vsca, vscr, vscexpt; + vector unsigned char vuca, vucr, vucexpt; + vector signed short int vssa, vssr, vssexpt; + vector unsigned short int vusa, vusr, vusexpt; + vector signed int vsia, vsir, vsiexpt; + vector unsigned int vuia, vuir, vuiexpt; + vector signed long long vslla, vsllr, vsllexpt; + vector unsigned long long vulla, vullr, vullexpt; + + vsca = (vector signed char) {0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15}; + + vscexpt = (vector signed char) {8, 0, 1, 0, 2, 0, 1, 0, + 3, 0, 1, 0, 2, 0, 1, 0}; + + vuca = (vector unsigned char) {'0', '3', '6', '9', 'A', 'B', 'E', 'F', + 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N'}; + + vucexpt = (vector unsigned char) {4, 0, 1, 0, 0, 1, 0, 1, + 0, 3, 0, 1, 0, 2, 0, 1}; + + vssa = (vector short int) {0x1, 0x10, 0x100, 0x1000, + 0x2, 0x20, 0x200, 0x2000}; + + vssexpt = (vector short int) {0, 4, 8, 12, 1, 5, 9, 13}; + + vusa = (vector unsigned short int) {0x4, 0x40, 0x400, 0x4000, + 0x8, 0x80, 0x800, 0x8000}; + vusexpt = (vector unsigned short int) {2, 6, 10, 14, 3, 7, 11, 15}; + + vsia = (vector int) {0x10000, 0x100000, 0x1000000, 0x10000000}; + vsiexpt = (vector int){16, 20, 24, 28}; + + vuia = (vector unsigned int) {0x2, 0x20, 0x200, 0x2000}; + vuiexpt = (vector unsigned int){1, 5, 9, 13}; + + vslla = (vector long long) {0x0000000000010000LL, 0x0001000100010000LL}; + vsllexpt = (vector long long){16, 16}; + + vulla = (vector unsigned long long) {0x0000400000000000LL, 0x0080000000000000ULL}; + + vullexpt = (vector unsigned long long) {46, 55}; + + vscr = vec_cnttz (vsca); + vucr = vec_cnttz (vuca); + vssr = vec_cnttz (vssa); + vusr = vec_cnttz (vusa); + vsir = vec_cnttz (vsia); + vuir = vec_cnttz (vuia); + vsllr = vec_cnttz (vslla); + vullr = vec_cnttz (vulla); + + for (i=0; i<16; i++) { + if (vscr[i] != vscexpt[i]) + abort(); + + if (vucr[i] != vucexpt[i]) + abort(); + } + + for (i=0; i<8; i++) { + if (vssr[i] != vssexpt[i]) + abort(); + + if (vusr[i] != vusexpt[i]) + abort(); + } + + for (i=0; i<4; i++) { + if (vsir[i] != vsiexpt[i]) + abort(); + + if (vuir[i] != vuiexpt[i]) + abort(); + } + + for (i=0; i<2; i++) { + if (vsllr[i] != vsllexpt[i]) + abort(); + + if (vullr[i] != vullexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/clone1.c b/gcc/testsuite/gcc.target/powerpc/clone1.c index 5c69db8e217..eb13a7b2dbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/clone1.c +++ b/gcc/testsuite/gcc.target/powerpc/clone1.c @@ -2,6 +2,7 @@ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ /* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 (aka, ISA 2.07) has to do modulus with divide and multiply. Make sure diff --git a/gcc/testsuite/gcc.target/powerpc/clone2.c b/gcc/testsuite/gcc.target/powerpc/clone2.c new file mode 100644 index 00000000000..ecad5eb8e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/clone2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ + +#include <stddef.h> +#include <stdlib.h> + +/* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 + (aka, ISA 2.07) has to do modulus with divide and multiply. Make sure that + the basic support for target_clones runs. + + Restrict ourselves to Linux, since IFUNC might not be supported in other + operating systems. */ + +__attribute__((__target_clones__("cpu=power9,default"))) +long mod_func (long a, long b) +{ + return a % b; +} + +#define X 53L +#define Y 7L +int +main (void) +{ + if (mod_func (X, Y) != (X % Y)) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c index 684c0f6d17d..c190f246231 100644 --- a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c @@ -4,6 +4,11 @@ void use_cpu_is_builtins (unsigned int *p) { + /* If GCC was configured to use an old GLIBC (before 2.23), the + __builtin_cpu_is and __builtin_cpu_supports built-in functions return 0, + and the compiler issues a warning that you need a newer glibc to use them. + Use #ifdef to avoid the warning. */ +#ifdef __BUILTIN_CPU_SUPPORTS__ p[0] = __builtin_cpu_is ("power9"); p[1] = __builtin_cpu_is ("power8"); p[2] = __builtin_cpu_is ("power7"); @@ -19,11 +24,15 @@ use_cpu_is_builtins (unsigned int *p) p[12] = __builtin_cpu_is ("ppc440"); p[13] = __builtin_cpu_is ("ppc405"); p[14] = __builtin_cpu_is ("ppc-cell-be"); +#else + p[0] = 0; +#endif } void use_cpu_supports_builtins (unsigned int *p) { +#ifdef __BUILTIN_CPU_SUPPORTS__ p[0] = __builtin_cpu_supports ("4xxmac"); p[1] = __builtin_cpu_supports ("altivec"); p[2] = __builtin_cpu_supports ("arch_2_05"); @@ -62,4 +71,9 @@ use_cpu_supports_builtins (unsigned int *p) p[35] = __builtin_cpu_supports ("ucache"); p[36] = __builtin_cpu_supports ("vcrypto"); p[37] = __builtin_cpu_supports ("vsx"); + p[38] = __builtin_cpu_supports ("darn"); + p[39] = __builtin_cpu_supports ("scv"); +#else + p[0] = 0; +#endif } diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c index 12623f20262..37a30d1c92f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-1.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c index 86d65b5b1fd..b4c4199c0b3 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-2.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c index b1c481fbf6d..c261c4e6f5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-3.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE vector double diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c new file mode 100644 index 00000000000..6add9038288 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c @@ -0,0 +1,24 @@ +/* This test is meant to verify that the gimple-folding does not + occur when the LHS portion of an expression is missing. + The intent of this test is to verify that we do not generate an ICE. + This was noticed during debug of PR81317. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector signed short +test1_nolhs (vector bool short x, vector signed short y) +{ + vec_add (x, y); + return vec_add (x, y); +} + +vector signed short +test2_nolhs (vector signed short x, vector bool short y) +{ + vec_add (x, y); + return vec_add (x, y); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-check.h b/gcc/testsuite/gcc.target/powerpc/mmx-check.h new file mode 100644 index 00000000000..e08077f6d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-check.h @@ -0,0 +1,35 @@ +#include <stdio.h> +#include <stdlib.h> + +static void mmx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + mmx_test (); +} + +int +main () + { +#ifdef __BUILTIN_CPU_SUPPORTS__ + /* Many MMX intrinsics are simpler / faster to implement by + transferring the __m64 (long int) to vector registers for SIMD + operations. To be efficient we also need the direct register + transfer instructions from POWER8. So we can test for + arch_2_07. */ + if ( __builtin_cpu_supports ("arch_2_07") ) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif +#endif /* __BUILTIN_CPU_SUPPORTS__ */ + return 0; + } diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packs.c b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c new file mode 100644 index 00000000000..18faa5a18eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c @@ -0,0 +1,91 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#include <mmintrin.h> +#include "mmx-check.h" + +#ifndef TEST +#define TEST mmx_test +#endif + +static void +__attribute__ ((noinline)) +check_packs_pu16 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pu16 ((__m64 ) src1, (__m64 ) src2); + + if (res != res_ref) + abort (); +} + +static void +__attribute__ ((noinline)) +check_packs_pi16 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pi16 ((__m64 ) src1, (__m64 ) src2); + + + if (res != res_ref) + abort (); +} + +static void +__attribute__ ((noinline)) +check_packs_pi32 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pi32 ((__m64 ) src1, (__m64 ) src2); + + if (res != res_ref) + abort (); +} + +static unsigned long long int src1[] = + { 0xffff0000fffe0000UL, 0x0001000000020000UL, 0xfffffffffffffffeUL, + 0x0000000100000002UL, 0x0001000200030004UL, 0xfffffffefffdfffcUL, + 0x0100020003000400UL, 0xff00fe01fe02fe03UL }; + +static unsigned long long int src2[] = + { 0xfffffffdfffffffcUL, 0x0000000200000003UL, 0xfffffffdfffffffcUL, + 0x0000000300000004UL, 0x0005000600070008UL, 0xfffbfffafff9fff8UL, + 0x0005000600070008UL, 0xfffbfffafff9fff8UL }; + +static unsigned long long int res_pi16[] = + { 0xfffdfffcff00fe00UL, 0x0002000301000200UL, 0xfffdfffcfffffffeUL, + 0x0003000400010002UL, 0x0506070801020304UL, 0xfbfaf9f8fffefdfcUL, + 0x050607087f7f7f7fUL, 0xfbfaf9f880808080UL }; + +static unsigned long long int res_pi32[] = + { 0xfffdfffc80008000UL, 0x000200037fff7fffUL, 0xfffdfffcfffffffeUL, + 0x0003000400010002UL, 0x7fff7fff7fff7fffUL, 0x80008000fffe8000UL, + 0x7fff7fff7fff7fffUL, 0x8000800080008000UL }; + +static unsigned long long int res_pu16[] = + { 0x0000000000000000UL, 0x0002000301000200UL, 0x0000000000000000UL, + 0x0003000400010002UL, 0x0506070801020304UL, 0x000000000000000UL, + 0x5060708ffffffffUL, 0x0000000000000000UL }; + +static void +TEST () +{ + long i; + + for (i = 0; i < 8; i++) + { + check_packs_pu16 (src1[i], src2[i], res_pu16[i]); + check_packs_pi16 (src1[i], src2[i], res_pi16[i]); + check_packs_pi32 (src1[i], src2[i], res_pi32[i]); + } +} + diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c new file mode 100644 index 00000000000..8698d55f012 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (2134, -128); + s2.as_m64 = _mm_set_pi32 (41124, 234); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + if (s1.as_int[i] > 32767) + e.as_short[i] = 32767; + else if (s1.as_int[i] < -32768) + e.as_short[i] = -32768; + else + e.as_short[i] = s1.as_int[i]; + } + + for (i = 0; i < 2; i++) + { + if (s2.as_int[i] > 32767) + e.as_short[i+2] = 32767; + else if (s2.as_int[i] < -32768) + e.as_short[i+2] = -32768; + else + e.as_short[i+2] = s2.as_int[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c new file mode 100644 index 00000000000..96bea7b81ab --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (2134, -128, 1234, 6354); + s2.as_m64 = _mm_set_pi16 (41124, 234, 2344, 2354); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + if (s1.as_short[i] > 127) + e.as_char[i] = 127; + else if (s1.as_short[i] < -128) + e.as_char[i] = -128; + else + e.as_char[i] = s1.as_short[i]; + } + + for (i = 0; i < 4; i++) + { + if (s2.as_short[i] > 127) + e.as_char[i+4] = 127; + else if (s2.as_short[i] < -128) + e.as_char[i+4] = -128; + else + e.as_char[i+4] = s2.as_short[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c new file mode 100644 index 00000000000..029d5687d71 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (-9, -10, -11, -12); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i=0; i<4; i++) + { + tmp = s1.as_short[i]<0 ? 0 : s1.as_short[i]; + tmp = tmp>255 ? 255 : tmp; + e.as_char[i] = tmp; + + tmp = s2.as_short[i]<0 ? 0 : s2.as_short[i]; + tmp = tmp>255 ? 255 : tmp; + e.as_char[i+4] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c new file mode 100644 index 00000000000..46b0584549e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = s1.as_char[i] + s2.as_char[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c new file mode 100644 index 00000000000..a006dda0ee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (30, 90); + s2.as_m64 = _mm_set_pi32 (76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] + s2.as_int[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c new file mode 100644 index 00000000000..5722302095e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_signed_char[i] + s2.as_signed_char[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e.as_signed_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c new file mode 100644 index 00000000000..f7518b4dbae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] + s2.as_short[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c new file mode 100644 index 00000000000..a209e3e30dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pu8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (30, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_char[i] + s2.as_char[i]; + + if (tmp > 255) + tmp = -1; + if (tmp < 0) + tmp = 0; + + e.as_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c new file mode 100644 index 00000000000..b46b7f636bb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = (unsigned short)s1.as_short[i] + (unsigned short)s2.as_short[i]; + + if (tmp > 65535) + tmp = -1; + + if (tmp < 0) + tmp = 0; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c new file mode 100644 index 00000000000..748fe2b5703 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 90); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] + s2.as_short[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c new file mode 100644 index 00000000000..c779b26e691 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 30, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = (s1.as_char[i] == s2.as_char[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c new file mode 100644 index 00000000000..a7807a2fdd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (98, 25); + s2.as_m64 = _mm_set_pi32 (98, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_int[i] == s2.as_int[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c new file mode 100644 index 00000000000..e25fd54c6b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (20, 30, 90, 80); + s2.as_m64 = _mm_set_pi16 (34, 78, 90, 6); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = (s1.as_short[i] == s2.as_short[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c new file mode 100644 index 00000000000..7f841b0b26e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 28, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = (s1.as_char[i] > s2.as_char[i]) ? -1 : 0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c new file mode 100644 index 00000000000..9f503b5ec9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (99, 25); + s2.as_m64 = _mm_set_pi32 (98, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_int[i] > s2.as_int[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c new file mode 100644 index 00000000000..85716937e0d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (20, 30, 90, 80); + s2.as_m64 = _mm_set_pi16 (34, 78, 90, 6); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = (s1.as_short[i] > s2.as_short[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c new file mode 100644 index 00000000000..220b4f65209 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_madd_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (2134, 3334, 1234, 6354); + s2.as_m64 = _mm_set_pi16 (1, 3, 4, 5); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_short[i * 2] * s2.as_short[i * 2]) + + (s1.as_short[(i * 2) + 1] * s2.as_short[(i * 2) + 1]); + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c new file mode 100644 index 00000000000..79b7c7b1838 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_mulhi_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 2067, -3033, 90); + s2.as_m64 = _mm_set_pi16 (11, 9834, 7444, -10222); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] * s2.as_short[i]; + + e.as_short[i] = (tmp & 0xffff0000)>>16; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c new file mode 100644 index 00000000000..6d041691772 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_mullo_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 2067, -3033, 90); + s2.as_m64 = _mm_set_pi16 (11, 9834, 7444, -10222); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] * s2.as_short[i]; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c new file mode 100644 index 00000000000..af687cd1e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sll_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1, -2); + u.as_m64 = test (s1.as_m64); + + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] << N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c new file mode 100644 index 00000000000..415f6a84176 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sll_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, 2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] << N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c new file mode 100644 index 00000000000..eaaf214292e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sra_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1000, -20000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c new file mode 100644 index 00000000000..eb7c3aec150 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sra_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, -2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c new file mode 100644 index 00000000000..1eb9d2897a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_srl_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1000, -20000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = (unsigned int)s1.as_int[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c new file mode 100644 index 00000000000..d066159e8eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_srl_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, -2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = (unsigned short)s1.as_short[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c new file mode 100644 index 00000000000..c64204afa41 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = s1.as_char[i] - s2.as_char[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c new file mode 100644 index 00000000000..3260f611748 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (30, 90); + s2.as_m64 = _mm_setr_pi32 (76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] - s2.as_int[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c new file mode 100644 index 00000000000..3f0fb2af899 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_signed_char[i] - s2.as_signed_char[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e.as_signed_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c new file mode 100644 index 00000000000..ae819e19c25 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 00); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] - s2.as_short[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c new file mode 100644 index 00000000000..bbdc0977109 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pu8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (30, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_char[i] - s2.as_char[i]; + + if (tmp > 255) + tmp = -1; + if (tmp < 0) + tmp = 0; + + e.as_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c new file mode 100644 index 00000000000..e26c380daee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 40); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = (unsigned short)s1.as_short[i] - (unsigned short)s2.as_short[i]; + + if (tmp > 65535) + tmp = -1; + + if (tmp < 0) + tmp = 0; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c new file mode 100644 index 00000000000..39e4cdea04a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 90); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] - s2.as_short[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c new file mode 100644 index 00000000000..dba56ca205b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + e.as_char[2*i] = s1.as_char[4+i]; + e.as_char[2*i + 1] = s2.as_char[4+i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c new file mode 100644 index 00000000000..f2f53c434c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + e.as_int[0] = s1.as_int[1]; + e.as_int[1] = s2.as_int[1]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c new file mode 100644 index 00000000000..f0264463a81 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + e.as_short[2*i] = s1.as_short[2+i]; + e.as_short[2*i + 1] = s2.as_short[2+i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c new file mode 100644 index 00000000000..36cf241ab19 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + e.as_char[2*i] = s1.as_char[i]; + e.as_char[2*i + 1] = s2.as_char[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c new file mode 100644 index 00000000000..8fb0251560a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + e.as_int[0] = s1.as_int[0]; + e.as_int[1] = s2.as_int[0]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c new file mode 100644 index 00000000000..37b6b6ff8c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + e.as_short[2*i] = s1.as_short[i]; + e.as_short[2*i + 1] = s2.as_short[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c index 33347740d0c..4b0370bb863 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c @@ -11,7 +11,8 @@ vector unsigned char vuca, vucb, vucc; vector bool char vbca, vbcb; vector unsigned short vusa, vusb; vector bool short vbsa, vbsb; -vector unsigned int vuia, vuib; +vector signed int vsia, vsib, vsic; +vector unsigned int vuia, vuib, vuic; vector bool int vbia, vbib; vector signed long long vsla, vslb; vector unsigned long long vula, vulb, vulc; @@ -24,6 +25,7 @@ void foo (vector unsigned char *vucr, vector bool char *vbcr, vector unsigned short *vusr, vector bool short *vbsr, + vector signed int *vsir, vector unsigned int *vuir, vector bool int *vbir, vector unsigned long long *vulr, @@ -32,10 +34,16 @@ void foo (vector unsigned char *vucr, vector unsigned __int128 *vuxr, vector double *vdr) { + *vsir++ = vec_addc (vsia, vsib); + *vuir++ = vec_addc (vuia, vuib); *vsxr++ = vec_addc (vsxa, vsxb); *vuxr++ = vec_addc (vuxa, vuxb); + *vsir++ = vec_adde (vsia, vsib, vsic); + *vuir++ = vec_adde (vuia, vuib, vuic); *vsxr++ = vec_adde (vsxa, vsxb, vsxc); *vuxr++ = vec_adde (vuxa, vuxb, vuxc); + *vsir++ = vec_addec (vsia, vsib, vsic); + *vuir++ = vec_addec (vuia, vuib, vuic); *vsxr++ = vec_addec (vsxa, vsxb, vsxc); *vuxr++ = vec_addec (vuxa, vuxb, vuxc); *vucr++ = vec_bperm (vuca, vucb); @@ -60,11 +68,30 @@ void foo (vector unsigned char *vucr, *vuxr++ = vec_pmsum_be (vula, vulb); *vuir++ = vec_shasigma_be (vuia, 0, 1); *vulr++ = vec_shasigma_be (vula, 0, 1); + *vsir++ = vec_subc (vsia, vsib); + *vuir++ = vec_subc (vuia, vuib); + *vsxr++ = vec_subc (vsxa, vsxb); + *vuxr++ = vec_subc (vuxa, vuxb); + *vsir++ = vec_sube (vsia, vsib, vsic); + *vuir++ = vec_sube (vuia, vuib, vuic); + *vsxr++ = vec_sube (vsxa, vsxb, vsxc); + *vuxr++ = vec_sube (vuxa, vuxb, vuxc); + *vsir++ = vec_subec (vsia, vsib, vsic); + *vuir++ = vec_subec (vuia, vuib, vuic); + *vsxr++ = vec_subec (vsxa, vsxb, vsxc); + *vuxr++ = vec_subec (vuxa, vuxb, vuxc); } /* { dg-final { scan-assembler-times "vaddcuq" 2 } } */ /* { dg-final { scan-assembler-times "vaddeuqm" 2 } } */ /* { dg-final { scan-assembler-times "vaddecuq" 2 } } */ +/* { dg-final { scan-assembler-times "vaddcuw" 6 } } */ +/* { dg-final { scan-assembler-times "vadduwm" 4 } } */ +/* { dg-final { scan-assembler-times "vsubcuq" 2 } } */ +/* { dg-final { scan-assembler-times "vsubeuqm" 2 } } */ +/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */ +/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */ /* { dg-final { scan-assembler-times "vbpermq" 2 } } */ /* { dg-final { scan-assembler-times "xxleqv" 4 } } */ /* { dg-final { scan-assembler-times "vgbbd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c index 17b73bbc7b3..7b30e4c4e23 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */ +/* { dg-options "-mcpu=power8 -O2 -fno-math-errno" } */ float abs_sf (float *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c index 23663b96da6..992ed225d5f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */ +/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c index 58e1f4485be..e683d614d62 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ +/* { dg-options "-mcpu=power8 -O2" } */ float load_store_sf (unsigned long num, diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c index c29b69d3e9e..64f0e31fb00 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify P9 changes to allow DImode into Altivec registers, and generate constants using XXSPLTIB. */ @@ -43,8 +43,8 @@ p9_minus_1 (void) return ret; } -/* { dg-final { scan-assembler "\[ \t\]xxspltib" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]mtvsrd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */ +/* { dg-final { scan-assembler {\mxxspltib\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mlfd\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mlxsd\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c index f33d18c6078..9e27936d748 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify that large integer constants are loaded via direct move instead of being loaded from memory. */ @@ -21,7 +21,7 @@ p9_large (void) return ret; } -/* { dg-final { scan-assembler "\[ \t\]mtvsrd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */ +/* { dg-final { scan-assembler {\mmtvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mlfd\M} } } */ +/* { dg-final { scan-assembler-not {\mlxsd\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c index af5b5905a6f..6e49606fe0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */ +/* { dg-options "-mcpu=power9 -O2 -mvsx-timode" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c index cd4ba7384de..164f11f6ea3 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c @@ -13,6 +13,12 @@ rev_char (vector char a) return vec_revb (a); /* XXBRQ. */ } +vector bool char +rev_bool_char (vector bool char a) +{ + return vec_revb (a); /* XXBRQ. */ +} + vector signed char rev_schar (vector signed char a) { @@ -31,6 +37,12 @@ rev_short (vector short a) return vec_revb (a); /* XXBRH. */ } +vector bool short +rev_bool_short (vector bool short a) +{ + return vec_revb (a); /* XXBRH. */ +} + vector unsigned short rev_ushort (vector unsigned short a) { @@ -43,6 +55,12 @@ rev_int (vector int a) return vec_revb (a); /* XXBRW. */ } +vector bool int +rev_bool_int (vector bool int a) +{ + return vec_revb (a); /* XXBRW. */ +} + vector unsigned int rev_uint (vector unsigned int a) { @@ -62,6 +80,6 @@ rev_double (vector double a) } /* { dg-final { scan-assembler-times "xxbrd" 1 } } */ -/* { dg-final { scan-assembler-times "xxbrh" 2 } } */ -/* { dg-final { scan-assembler-times "xxbrq" 3 } } */ -/* { dg-final { scan-assembler-times "xxbrw" 3 } } */ +/* { dg-final { scan-assembler-times "xxbrh" 3 } } */ +/* { dg-final { scan-assembler-times "xxbrq" 4 } } */ +/* { dg-final { scan-assembler-times "xxbrw" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c index 97f6186bf91..a4a19390d7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c @@ -20,6 +20,18 @@ rev_ulong (vector unsigned long a) return vec_revb (a); /* XXBRD. */ } +vector long long +rev_long_long (vector long long a) +{ + return vec_revb (a); /* XXBRD. */ +} + +vector unsigned long long +rev_ulong_ulong (vector unsigned long long a) +{ + return vec_revb (a); /* XXBRD. */ +} + vector __int128_t rev_int128 (vector __int128_t a) { @@ -32,5 +44,5 @@ rev_uint128 (vector __uint128_t a) return vec_revb (a); /* XXBRQ. */ } -/* { dg-final { scan-assembler-times "xxbrd" 2 } } */ +/* { dg-final { scan-assembler-times "xxbrd" 4 } } */ /* { dg-final { scan-assembler-times "xxbrq" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c index 2efa952a239..de508b784c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c @@ -2,15 +2,13 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ -/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fcfids " 3 } } */ -/* { dg-final { scan-assembler-times "fcfidus " 1 } } */ -/* { dg-final { scan-assembler-times "fcfid " 3 } } */ -/* { dg-final { scan-assembler-times "fcfidu " 1 } } */ -/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ -/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfcfidus\M|\mxscvuxdsp\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfcfidu\M|\mxscvuxddp\M} 1 } } */ void int_to_float (float *dest, int *src) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c index 9e192d13398..cb6dea41b06 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c @@ -2,8 +2,8 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler "friz" } } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler {\mfriz\M|\mxsrdpiz\M} } } */ double round_double_llong (double a) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c index b59cac3a5bb..6bffa164fcd 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c @@ -2,13 +2,11 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fctidz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiduz " 2 } } */ -/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ -/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiduz\M|\mxscvdpuxds\M} 2 } } */ void float_to_int (int *dest, float src) { *dest = (int) src; } void double_to_int (int *dest, double src) { *dest = (int) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c index 372b2334686..d376936a750 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c @@ -2,12 +2,12 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "fctidz" 2 } } */ -/* { dg-final { scan-assembler-not "lwz" } } */ -/* { dg-final { scan-assembler-not "stw" } } */ -/* { dg-final { scan-assembler-not "ld " } } */ -/* { dg-final { scan-assembler-not "std" } } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlwz\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mstd\M} } } */ void float_to_llong (long long *dest, float src) { *dest = (long long) src; } void double_to_llong (long long *dest, double src) { *dest = (long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c index 0cfa0da2a72..50ab078f55a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -2,15 +2,15 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "stfiwx" 4 } } */ -/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ -/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fcfids " 2 } } */ -/* { dg-final { scan-assembler-not "lwz" } } */ -/* { dg-final { scan-assembler-not "stw" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlwz\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ /* Make sure we don't have loads/stores to the GPR unit. */ double diff --git a/gcc/testsuite/gcc.target/powerpc/pr63491.c b/gcc/testsuite/gcc.target/powerpc/pr63491.c index a1518912308..be6a40eb32d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63491.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63491.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-options "-O1 -mcpu=power8 -mlra" } */ +/* { dg-options "-O1 -mcpu=power8" } */ typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; typedef unsigned long long scalar_64_t; diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c b/gcc/testsuite/gcc.target/powerpc/pr65849-1.c deleted file mode 100644 index 288fdeed2ca..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c +++ /dev/null @@ -1,728 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */ - -/* Test whether we can enable the -mupper-regs-df with target pragmas. Make - sure double values are allocated to the Altivec registers as well as the - traditional FPR registers. */ - -#ifndef TYPE -#define TYPE double -#endif - -#ifndef MASK_TYPE -#define MASK_TYPE unsigned long long -#endif - -#define MASK_ONE ((MASK_TYPE)1) -#define ZERO ((TYPE) 0.0) - -#pragma GCC target ("upper-regs-df") -TYPE -test_add (const MASK_TYPE *add_mask, const TYPE *add_values, - const MASK_TYPE *sub_mask, const TYPE *sub_values, - const MASK_TYPE *mul_mask, const TYPE *mul_values, - const MASK_TYPE *div_mask, const TYPE *div_values, - const MASK_TYPE *eq0_mask, int *eq0_ptr) -{ - TYPE value; - TYPE value00 = ZERO; - TYPE value01 = ZERO; - TYPE value02 = ZERO; - TYPE value03 = ZERO; - TYPE value04 = ZERO; - TYPE value05 = ZERO; - TYPE value06 = ZERO; - TYPE value07 = ZERO; - TYPE value08 = ZERO; - TYPE value09 = ZERO; - TYPE value10 = ZERO; - TYPE value11 = ZERO; - TYPE value12 = ZERO; - TYPE value13 = ZERO; - TYPE value14 = ZERO; - TYPE value15 = ZERO; - TYPE value16 = ZERO; - TYPE value17 = ZERO; - TYPE value18 = ZERO; - TYPE value19 = ZERO; - TYPE value20 = ZERO; - TYPE value21 = ZERO; - TYPE value22 = ZERO; - TYPE value23 = ZERO; - TYPE value24 = ZERO; - TYPE value25 = ZERO; - TYPE value26 = ZERO; - TYPE value27 = ZERO; - TYPE value28 = ZERO; - TYPE value29 = ZERO; - TYPE value30 = ZERO; - TYPE value31 = ZERO; - TYPE value32 = ZERO; - TYPE value33 = ZERO; - TYPE value34 = ZERO; - TYPE value35 = ZERO; - TYPE value36 = ZERO; - TYPE value37 = ZERO; - TYPE value38 = ZERO; - TYPE value39 = ZERO; - MASK_TYPE mask; - int eq0; - - while ((mask = *add_mask++) != 0) - { - value = *add_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 += value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 += value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 += value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 += value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 += value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 += value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 += value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 += value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 += value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 += value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 += value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 += value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 += value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 += value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 += value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 += value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 += value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 += value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 += value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 += value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 += value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 += value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 += value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 += value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 += value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 += value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 += value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 += value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 += value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 += value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 += value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 += value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 += value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 += value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 += value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 += value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 += value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 += value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 += value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 += value; - } - - while ((mask = *sub_mask++) != 0) - { - value = *sub_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 -= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 -= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 -= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 -= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 -= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 -= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 -= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 -= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 -= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 -= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 -= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 -= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 -= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 -= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 -= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 -= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 -= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 -= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 -= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 -= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 -= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 -= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 -= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 -= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 -= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 -= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 -= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 -= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 -= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 -= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 -= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 -= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 -= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 -= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 -= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 -= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 -= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 -= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 -= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 -= value; - } - - while ((mask = *mul_mask++) != 0) - { - value = *mul_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 *= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 *= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 *= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 *= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 *= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 *= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 *= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 *= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 *= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 *= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 *= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 *= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 *= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 *= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 *= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 *= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 *= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 *= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 *= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 *= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 *= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 *= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 *= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 *= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 *= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 *= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 *= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 *= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 *= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 *= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 *= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 *= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 *= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 *= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 *= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 *= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 *= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 *= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 *= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 *= value; - } - - while ((mask = *div_mask++) != 0) - { - value = *div_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 /= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 /= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 /= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 /= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 /= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 /= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 /= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 /= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 /= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 /= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 /= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 /= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 /= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 /= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 /= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 /= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 /= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 /= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 /= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 /= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 /= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 /= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 /= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 /= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 /= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 /= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 /= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 /= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 /= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 /= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 /= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 /= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 /= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 /= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 /= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 /= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 /= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 /= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 /= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 /= value; - } - - while ((mask = *eq0_mask++) != 0) - { - eq0 = 0; - - if ((mask & (MASK_ONE << 0)) != 0) - eq0 |= (value00 == ZERO); - - if ((mask & (MASK_ONE << 1)) != 0) - eq0 |= (value01 == ZERO); - - if ((mask & (MASK_ONE << 2)) != 0) - eq0 |= (value02 == ZERO); - - if ((mask & (MASK_ONE << 3)) != 0) - eq0 |= (value03 == ZERO); - - if ((mask & (MASK_ONE << 4)) != 0) - eq0 |= (value04 == ZERO); - - if ((mask & (MASK_ONE << 5)) != 0) - eq0 |= (value05 == ZERO); - - if ((mask & (MASK_ONE << 6)) != 0) - eq0 |= (value06 == ZERO); - - if ((mask & (MASK_ONE << 7)) != 0) - eq0 |= (value07 == ZERO); - - if ((mask & (MASK_ONE << 8)) != 0) - eq0 |= (value08 == ZERO); - - if ((mask & (MASK_ONE << 9)) != 0) - eq0 |= (value09 == ZERO); - - if ((mask & (MASK_ONE << 10)) != 0) - eq0 |= (value10 == ZERO); - - if ((mask & (MASK_ONE << 11)) != 0) - eq0 |= (value11 == ZERO); - - if ((mask & (MASK_ONE << 12)) != 0) - eq0 |= (value12 == ZERO); - - if ((mask & (MASK_ONE << 13)) != 0) - eq0 |= (value13 == ZERO); - - if ((mask & (MASK_ONE << 14)) != 0) - eq0 |= (value14 == ZERO); - - if ((mask & (MASK_ONE << 15)) != 0) - eq0 |= (value15 == ZERO); - - if ((mask & (MASK_ONE << 16)) != 0) - eq0 |= (value16 == ZERO); - - if ((mask & (MASK_ONE << 17)) != 0) - eq0 |= (value17 == ZERO); - - if ((mask & (MASK_ONE << 18)) != 0) - eq0 |= (value18 == ZERO); - - if ((mask & (MASK_ONE << 19)) != 0) - eq0 |= (value19 == ZERO); - - if ((mask & (MASK_ONE << 20)) != 0) - eq0 |= (value20 == ZERO); - - if ((mask & (MASK_ONE << 21)) != 0) - eq0 |= (value21 == ZERO); - - if ((mask & (MASK_ONE << 22)) != 0) - eq0 |= (value22 == ZERO); - - if ((mask & (MASK_ONE << 23)) != 0) - eq0 |= (value23 == ZERO); - - if ((mask & (MASK_ONE << 24)) != 0) - eq0 |= (value24 == ZERO); - - if ((mask & (MASK_ONE << 25)) != 0) - eq0 |= (value25 == ZERO); - - if ((mask & (MASK_ONE << 26)) != 0) - eq0 |= (value26 == ZERO); - - if ((mask & (MASK_ONE << 27)) != 0) - eq0 |= (value27 == ZERO); - - if ((mask & (MASK_ONE << 28)) != 0) - eq0 |= (value28 == ZERO); - - if ((mask & (MASK_ONE << 29)) != 0) - eq0 |= (value29 == ZERO); - - if ((mask & (MASK_ONE << 30)) != 0) - eq0 |= (value30 == ZERO); - - if ((mask & (MASK_ONE << 31)) != 0) - eq0 |= (value31 == ZERO); - - if ((mask & (MASK_ONE << 32)) != 0) - eq0 |= (value32 == ZERO); - - if ((mask & (MASK_ONE << 33)) != 0) - eq0 |= (value33 == ZERO); - - if ((mask & (MASK_ONE << 34)) != 0) - eq0 |= (value34 == ZERO); - - if ((mask & (MASK_ONE << 35)) != 0) - eq0 |= (value35 == ZERO); - - if ((mask & (MASK_ONE << 36)) != 0) - eq0 |= (value36 == ZERO); - - if ((mask & (MASK_ONE << 37)) != 0) - eq0 |= (value37 == ZERO); - - if ((mask & (MASK_ONE << 38)) != 0) - eq0 |= (value38 == ZERO); - - if ((mask & (MASK_ONE << 39)) != 0) - eq0 |= (value39 == ZERO); - - *eq0_ptr++ = eq0; - } - - return ( value00 + value01 + value02 + value03 + value04 - + value05 + value06 + value07 + value08 + value09 - + value10 + value11 + value12 + value13 + value14 - + value15 + value16 + value17 + value18 + value19 - + value20 + value21 + value22 + value23 + value24 - + value25 + value26 + value27 + value28 + value29 - + value30 + value31 + value32 + value33 + value34 - + value35 + value36 + value37 + value38 + value39); -} - -/* { dg-final { scan-assembler "fadd" } } */ -/* { dg-final { scan-assembler "fsub" } } */ -/* { dg-final { scan-assembler "fmul" } } */ -/* { dg-final { scan-assembler "fdiv" } } */ -/* { dg-final { scan-assembler "fcmpu" } } */ -/* { dg-final { scan-assembler "xsadddp" } } */ -/* { dg-final { scan-assembler "xssubdp" } } */ -/* { dg-final { scan-assembler "xsmuldp" } } */ -/* { dg-final { scan-assembler "xsdivdp" } } */ -/* { dg-final { scan-assembler "xscmpudp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c b/gcc/testsuite/gcc.target/powerpc/pr65849-2.c deleted file mode 100644 index 0af6a4a51c7..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c +++ /dev/null @@ -1,728 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* Test whether we can enable the -mupper-regs-sf with target pragmas. Make - sure float values are allocated to the Altivec registers as well as the - traditional FPR registers. */ - -#ifndef TYPE -#define TYPE float -#endif - -#ifndef MASK_TYPE -#define MASK_TYPE unsigned long long -#endif - -#define MASK_ONE ((MASK_TYPE)1) -#define ZERO ((TYPE) 0.0) - -#pragma GCC target ("upper-regs-sf") -TYPE -test_add (const MASK_TYPE *add_mask, const TYPE *add_values, - const MASK_TYPE *sub_mask, const TYPE *sub_values, - const MASK_TYPE *mul_mask, const TYPE *mul_values, - const MASK_TYPE *div_mask, const TYPE *div_values, - const MASK_TYPE *eq0_mask, int *eq0_ptr) -{ - TYPE value; - TYPE value00 = ZERO; - TYPE value01 = ZERO; - TYPE value02 = ZERO; - TYPE value03 = ZERO; - TYPE value04 = ZERO; - TYPE value05 = ZERO; - TYPE value06 = ZERO; - TYPE value07 = ZERO; - TYPE value08 = ZERO; - TYPE value09 = ZERO; - TYPE value10 = ZERO; - TYPE value11 = ZERO; - TYPE value12 = ZERO; - TYPE value13 = ZERO; - TYPE value14 = ZERO; - TYPE value15 = ZERO; - TYPE value16 = ZERO; - TYPE value17 = ZERO; - TYPE value18 = ZERO; - TYPE value19 = ZERO; - TYPE value20 = ZERO; - TYPE value21 = ZERO; - TYPE value22 = ZERO; - TYPE value23 = ZERO; - TYPE value24 = ZERO; - TYPE value25 = ZERO; - TYPE value26 = ZERO; - TYPE value27 = ZERO; - TYPE value28 = ZERO; - TYPE value29 = ZERO; - TYPE value30 = ZERO; - TYPE value31 = ZERO; - TYPE value32 = ZERO; - TYPE value33 = ZERO; - TYPE value34 = ZERO; - TYPE value35 = ZERO; - TYPE value36 = ZERO; - TYPE value37 = ZERO; - TYPE value38 = ZERO; - TYPE value39 = ZERO; - MASK_TYPE mask; - int eq0; - - while ((mask = *add_mask++) != 0) - { - value = *add_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 += value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 += value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 += value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 += value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 += value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 += value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 += value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 += value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 += value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 += value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 += value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 += value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 += value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 += value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 += value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 += value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 += value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 += value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 += value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 += value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 += value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 += value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 += value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 += value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 += value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 += value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 += value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 += value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 += value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 += value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 += value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 += value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 += value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 += value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 += value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 += value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 += value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 += value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 += value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 += value; - } - - while ((mask = *sub_mask++) != 0) - { - value = *sub_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 -= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 -= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 -= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 -= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 -= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 -= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 -= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 -= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 -= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 -= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 -= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 -= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 -= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 -= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 -= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 -= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 -= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 -= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 -= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 -= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 -= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 -= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 -= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 -= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 -= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 -= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 -= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 -= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 -= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 -= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 -= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 -= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 -= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 -= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 -= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 -= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 -= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 -= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 -= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 -= value; - } - - while ((mask = *mul_mask++) != 0) - { - value = *mul_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 *= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 *= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 *= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 *= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 *= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 *= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 *= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 *= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 *= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 *= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 *= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 *= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 *= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 *= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 *= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 *= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 *= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 *= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 *= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 *= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 *= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 *= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 *= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 *= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 *= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 *= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 *= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 *= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 *= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 *= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 *= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 *= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 *= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 *= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 *= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 *= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 *= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 *= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 *= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 *= value; - } - - while ((mask = *div_mask++) != 0) - { - value = *div_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 /= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 /= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 /= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 /= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 /= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 /= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 /= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 /= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 /= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 /= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 /= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 /= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 /= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 /= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 /= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 /= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 /= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 /= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 /= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 /= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 /= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 /= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 /= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 /= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 /= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 /= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 /= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 /= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 /= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 /= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 /= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 /= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 /= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 /= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 /= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 /= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 /= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 /= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 /= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 /= value; - } - - while ((mask = *eq0_mask++) != 0) - { - eq0 = 0; - - if ((mask & (MASK_ONE << 0)) != 0) - eq0 |= (value00 == ZERO); - - if ((mask & (MASK_ONE << 1)) != 0) - eq0 |= (value01 == ZERO); - - if ((mask & (MASK_ONE << 2)) != 0) - eq0 |= (value02 == ZERO); - - if ((mask & (MASK_ONE << 3)) != 0) - eq0 |= (value03 == ZERO); - - if ((mask & (MASK_ONE << 4)) != 0) - eq0 |= (value04 == ZERO); - - if ((mask & (MASK_ONE << 5)) != 0) - eq0 |= (value05 == ZERO); - - if ((mask & (MASK_ONE << 6)) != 0) - eq0 |= (value06 == ZERO); - - if ((mask & (MASK_ONE << 7)) != 0) - eq0 |= (value07 == ZERO); - - if ((mask & (MASK_ONE << 8)) != 0) - eq0 |= (value08 == ZERO); - - if ((mask & (MASK_ONE << 9)) != 0) - eq0 |= (value09 == ZERO); - - if ((mask & (MASK_ONE << 10)) != 0) - eq0 |= (value10 == ZERO); - - if ((mask & (MASK_ONE << 11)) != 0) - eq0 |= (value11 == ZERO); - - if ((mask & (MASK_ONE << 12)) != 0) - eq0 |= (value12 == ZERO); - - if ((mask & (MASK_ONE << 13)) != 0) - eq0 |= (value13 == ZERO); - - if ((mask & (MASK_ONE << 14)) != 0) - eq0 |= (value14 == ZERO); - - if ((mask & (MASK_ONE << 15)) != 0) - eq0 |= (value15 == ZERO); - - if ((mask & (MASK_ONE << 16)) != 0) - eq0 |= (value16 == ZERO); - - if ((mask & (MASK_ONE << 17)) != 0) - eq0 |= (value17 == ZERO); - - if ((mask & (MASK_ONE << 18)) != 0) - eq0 |= (value18 == ZERO); - - if ((mask & (MASK_ONE << 19)) != 0) - eq0 |= (value19 == ZERO); - - if ((mask & (MASK_ONE << 20)) != 0) - eq0 |= (value20 == ZERO); - - if ((mask & (MASK_ONE << 21)) != 0) - eq0 |= (value21 == ZERO); - - if ((mask & (MASK_ONE << 22)) != 0) - eq0 |= (value22 == ZERO); - - if ((mask & (MASK_ONE << 23)) != 0) - eq0 |= (value23 == ZERO); - - if ((mask & (MASK_ONE << 24)) != 0) - eq0 |= (value24 == ZERO); - - if ((mask & (MASK_ONE << 25)) != 0) - eq0 |= (value25 == ZERO); - - if ((mask & (MASK_ONE << 26)) != 0) - eq0 |= (value26 == ZERO); - - if ((mask & (MASK_ONE << 27)) != 0) - eq0 |= (value27 == ZERO); - - if ((mask & (MASK_ONE << 28)) != 0) - eq0 |= (value28 == ZERO); - - if ((mask & (MASK_ONE << 29)) != 0) - eq0 |= (value29 == ZERO); - - if ((mask & (MASK_ONE << 30)) != 0) - eq0 |= (value30 == ZERO); - - if ((mask & (MASK_ONE << 31)) != 0) - eq0 |= (value31 == ZERO); - - if ((mask & (MASK_ONE << 32)) != 0) - eq0 |= (value32 == ZERO); - - if ((mask & (MASK_ONE << 33)) != 0) - eq0 |= (value33 == ZERO); - - if ((mask & (MASK_ONE << 34)) != 0) - eq0 |= (value34 == ZERO); - - if ((mask & (MASK_ONE << 35)) != 0) - eq0 |= (value35 == ZERO); - - if ((mask & (MASK_ONE << 36)) != 0) - eq0 |= (value36 == ZERO); - - if ((mask & (MASK_ONE << 37)) != 0) - eq0 |= (value37 == ZERO); - - if ((mask & (MASK_ONE << 38)) != 0) - eq0 |= (value38 == ZERO); - - if ((mask & (MASK_ONE << 39)) != 0) - eq0 |= (value39 == ZERO); - - *eq0_ptr++ = eq0; - } - - return ( value00 + value01 + value02 + value03 + value04 - + value05 + value06 + value07 + value08 + value09 - + value10 + value11 + value12 + value13 + value14 - + value15 + value16 + value17 + value18 + value19 - + value20 + value21 + value22 + value23 + value24 - + value25 + value26 + value27 + value28 + value29 - + value30 + value31 + value32 + value33 + value34 - + value35 + value36 + value37 + value38 + value39); -} - -/* { dg-final { scan-assembler "fadds" } } */ -/* { dg-final { scan-assembler "fsubs" } } */ -/* { dg-final { scan-assembler "fmuls" } } */ -/* { dg-final { scan-assembler "fdivs" } } */ -/* { dg-final { scan-assembler "fcmpu" } } */ -/* { dg-final { scan-assembler "xsaddsp" } } */ -/* { dg-final { scan-assembler "xssubsp" } } */ -/* { dg-final { scan-assembler "xsmulsp" } } */ -/* { dg-final { scan-assembler "xsdivsp" } } */ -/* { dg-final { scan-assembler "xscmpudp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c index 16b309c151e..3ee8003bebc 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr67808.c +++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O1 -mvsx -mlra -mcpu=power7 -mlong-double-128" } */ +/* { dg-options "-O1 -mvsx -mcpu=power7 -mlong-double-128" } */ /* PR 67808: LRA ICEs on simple double to long double conversion test case */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr68805.c b/gcc/testsuite/gcc.target/powerpc/pr68805.c index 5510811107d..f4454a9e2d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr68805.c +++ b/gcc/testsuite/gcc.target/powerpc/pr68805.c @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc64le-*-* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-O2 -mvsx-timode -mcpu=power8 -mlra" } */ +/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */ typedef struct bar { void *a; diff --git a/gcc/testsuite/gcc.target/powerpc/pr69461.c b/gcc/testsuite/gcc.target/powerpc/pr69461.c index 406e7049d29..f693a5f0146 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr69461.c +++ b/gcc/testsuite/gcc.target/powerpc/pr69461.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mlra" } */ +/* { dg-options "-O3" } */ extern void _setjmp (void); typedef struct { diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c index fa6b4ffb816..1cb809f8b2a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector" } */ typedef __attribute__((altivec(vector__))) int type_t; type_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c index 99855fa1667..f953ebe4f9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */ +/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -funroll-loops -fno-aggressive-loop-optimizations" } */ typedef double vec[3]; struct vec_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71680.c b/gcc/testsuite/gcc.target/powerpc/pr71680.c index fe5260f73d9..cdb7b5143ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71680.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71680.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mlra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ #pragma pack(1) struct diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c index c752f64e1c7..eba47b0951f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71698.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target dfp } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9" } */ extern void testvad128 (int n, ...); void diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c index a0c330db931..732daf97595 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71720.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr72853.c b/gcc/testsuite/gcc.target/powerpc/pr72853.c index 8a086087088..9dc1bd2344c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72853.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72853.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */ +/* { dg-options "-mcpu=power9 -O3 -funroll-loops" } */ /* derived from 20021120-1.c, compiled for -mcpu=power9. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c index 295aa27acdc..474bdbf0b16 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr77289.c +++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */ +/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mupdate -fno-auto-inc-dec" } */ /* PR 77289: LRA ICEs due to invalid constraint checking. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78458.c b/gcc/testsuite/gcc.target/powerpc/pr78458.c index 777ac43bcad..a27876375af 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78458.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78458.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe" } */ /* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ extern void bar (void); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78543.c b/gcc/testsuite/gcc.target/powerpc/pr78543.c index 0421344d3ce..13b34e58a0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78543.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78543.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mno-lra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ typedef long a; enum c { e, f, g, h, i, ab } j(); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78953.c b/gcc/testsuite/gcc.target/powerpc/pr78953.c index 34a3083918d..fd26f073499 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78953.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78953.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ #include <altivec.h> @@ -16,4 +16,4 @@ foo (vector int *vp, int *ip) ip[4] = vec_extract (v, 0); } -/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */ +/* { dg-final { scan-assembler {\mxxextractuw\M|\mvextuw[lr]x\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr79907.c b/gcc/testsuite/gcc.target/powerpc/pr79907.c index c0e669b3264..240a1f46713 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79907.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79907.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O3 -mno-upper-regs-df" } */ +/* { dg-options "-mcpu=power8 -O3" } */ int foo (short a[], int x) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-1.c b/gcc/testsuite/gcc.target/powerpc/pr80099-1.c deleted file mode 100644 index 9f34c5fbef8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* PR target/80099: compiler internal error if -mno-upper-regs-sf used. */ - -int a; -int int_from_mem (vector float *c) -{ - return __builtin_vec_extract (*c, a); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-2.c b/gcc/testsuite/gcc.target/powerpc/pr80099-2.c deleted file mode 100644 index 5800db63212..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-2.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-3.c b/gcc/testsuite/gcc.target/powerpc/pr80099-3.c deleted file mode 100644 index 71c2b40b0d1..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-3.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-df" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-4.c b/gcc/testsuite/gcc.target/powerpc/pr80099-4.c deleted file mode 100644 index 145dd1724af..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-4.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-5.c b/gcc/testsuite/gcc.target/powerpc/pr80099-5.c deleted file mode 100644 index 9ebc0fe466d..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-5.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80103-1.c b/gcc/testsuite/gcc.target/powerpc/pr80103-1.c index 35d48c4d8ce..bbec707df20 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80103-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80103-1.c @@ -12,5 +12,5 @@ int a; void b (__attribute__ ((__vector_size__ (16))) char c) { - a = ((__attributes__ ((__vector_size__ (2 * sizeof (long)))) long) c)[0]; + a = ((__attribute__ ((__vector_size__ (2 * sizeof (long)))) long) c)[0]; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr81348.c b/gcc/testsuite/gcc.target/powerpc/pr81348.c new file mode 100644 index 00000000000..e8e10bb598b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr81348.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -Og" } */ + +/* PR target/81348: Compiler died in doing short->float conversion due to using + the wrong register in a define_split. */ + +int a; +short b; +float ***c; + +void d(void) +{ + int e = 3; + + if (a) + e = b; + + ***c = e; +} + +/* { dg-final { scan-assembler {\mlxsihzx\M} } } */ +/* { dg-final { scan-assembler {\mvextsh2d\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c index 17f01bfbfca..0df579797ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c @@ -2,10 +2,10 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */ +/* { dg-options "-mcpu=power7 -O2" } */ -/* Test for the -mupper-regs-df option to make sure double values are allocated - to the Altivec registers as well as the traditional FPR registers. */ +/* Test to make sure double values are allocated to the Altivec registers as + well as the traditional FPR registers. */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c index 8c246796805..fd29fb5fd6e 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c @@ -2,10 +2,10 @@ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ +/* { dg-options "-mcpu=power8 -O2" } */ -/* Test for the -mupper-regs-df option to make sure double values are allocated - to the Altivec registers as well as the traditional FPR registers. */ +/* Test make sure single precision values are allocated to the Altivec + registers as well as the traditional FPR registers. */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c index 2f9624d4c86..9c8e6f3a684 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c index d6d546942da..f4a536a2ea9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector long merge (long a, long b) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c index 14e605ca435..8d610e158cc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ vector int merge (int a, int b, int c, int d) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c index b5e531ea7f1..c44fa9b2a3d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ vector int splat (int a) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c index 2da79ef9e9d..5df260ded29 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector char insert_0_0 (vector char v) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c index dc97ac9d4d3..deaa6acfa6e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector int insert_0_0 (vector int v) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c index d82760955fd..eabcf3488de 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector short insert_0_0 (vector short v) diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c index 8f710e5c5bd..2a4e610de72 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_d_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c index e6f26a8e014..6ee08cf109a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ unsigned int foo (unsigned short u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c index 3c0e66d14ca..972be677dd6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_v_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c index a252457f314..1c224cb1b61 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_d_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c index d321970d0ac..478c9da3051 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ unsigned int foo (unsigned char u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c index 50142e8d86d..6537d8b80a0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_v_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c index 91d55bb8791..77049008845 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ double load_asm_d_constraint (int *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c index 56793a16222..92053d9ac35 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ unsigned int foo (unsigned int u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c index a35e6db0b79..62f5ab46c04 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ double load_asm_v_constraint (int *p) { diff --git a/gcc/testsuite/gcc.target/s390/nodatarel-1.c b/gcc/testsuite/gcc.target/s390/nodatarel-1.c new file mode 100644 index 00000000000..1d589a10947 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/nodatarel-1.c @@ -0,0 +1,83 @@ +/* Test -mno-pic-data-is-text-relative option. No relative addressing + of elements in .data and .bss are allowed with that option. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -fno-optimize-sibling-calls -fpic -mno-pic-data-is-text-relative -march=z10 -mtune=z9-109 -mzarch" } */ + +static int a = 3; + +/* With -mno-pic-data-is-text-relative these must be addressed via + GOT. */ + +int __attribute__((noinline,noclone)) +foo () +{ + return a; +} + +static int __attribute__((noinline,noclone)) +foostatic (void) +{ + return a; +} + +/* Just to make a potentially modified. */ + +void +bar (int b) +{ + a = b; +} + +/* { dg-final { scan-assembler-times "a@GOTENT" 3 } } */ + +/* The exrl target is a label_ref which should not be affected at + all. */ + +void +mymemcpy (char *dst, char *src, long size) +{ + __builtin_memcpy (dst, src, size); +} + +/* { dg-final { scan-assembler "exrl" } } */ + + +/* PLT slots can still be addressed relatively. */ + +int +callfoo () +{ + return foo (); +} + +/* { dg-final { scan-assembler-times "foo@PLT" 1 } } */ + + +/* GOT entries can still be addressed relatively. */ + +void * +fooptr () +{ + return &foo; +} + +/* { dg-final { scan-assembler-times "foo@GOTENT" 1 } } */ + + +/* A static function can be addressed relatively. */ + +int +callfoostatic () +{ + return foostatic (); +} + +void * +foostaticptr () +{ + return &foostatic; +} + + +/* { dg-final { scan-assembler-not "foostatic@" } } */ diff --git a/gcc/testsuite/gcc.target/s390/pr81534.c b/gcc/testsuite/gcc.target/s390/pr81534.c new file mode 100644 index 00000000000..0e1bd99b9cb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr81534.c @@ -0,0 +1,17 @@ +/* PR81534 This testcase used to fail because the HI/QI + "atomic_fetch_<atomic><mode>" expander accepted symbolic references + and emitted CAS patterns whose insn definition rejected them. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -march=zEC12" } */ + +struct { + short b; + long c; +} a = {}; + +void +d () +{ + __atomic_fetch_add(&a.b, 0, 5); +} diff --git a/gcc/testsuite/gcc.target/sparc/dictunpack.c b/gcc/testsuite/gcc.target/sparc/dictunpack.c new file mode 100644 index 00000000000..4334dee2b2e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/dictunpack.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4b" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +vec8 test_dictunpack8 (double a) +{ + return __builtin_vis_dictunpack8 (a, 6); +} + +vec16 test_dictunpack16 (double a) +{ + return __builtin_vis_dictunpack16 (a, 14); +} + +vec32 test_dictunpack32 (double a) +{ + return __builtin_vis_dictunpack32 (a, 30); +} + +/* { dg-final { scan-assembler "dictunpack\t%" } } */ +/* { dg-final { scan-assembler "dictunpack\t%" } } */ +/* { dg-final { scan-assembler "dictunpack\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c b/gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c new file mode 100644 index 00000000000..3e3daa6e99f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4b" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmpde8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpde8shl (a, b, 2); +} + +long test_fpcmpde16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpde16shl (a, b, 2); +} + +long test_fpcmpde32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpde32shl (a, b, 2); +} + +/* { dg-final { scan-assembler "fpcmpde8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpde16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpde32shl\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpshl.c b/gcc/testsuite/gcc.target/sparc/fpcmpshl.c new file mode 100644 index 00000000000..0985251cbfd --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpshl.c @@ -0,0 +1,81 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4b" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmple8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmple8shl (a, b, 2); +} + +long test_fpcmpgt8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpgt8shl (a, b, 2); +} + +long test_fpcmpeq8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpeq8shl (a, b, 2); +} + +long test_fpcmpne8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpne8shl (a, b, 2); +} + +long test_fpcmple16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmple16shl (a, b, 2); +} + +long test_fpcmpgt16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpgt16shl (a, b, 2); +} + +long test_fpcmpeq16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpeq16shl (a, b, 2); +} + +long test_fpcmpne16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpne16shl (a, b, 2); +} + +long test_fpcmple32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmple32shl (a, b, 2); +} + +long test_fpcmpgt32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpgt32shl (a, b, 2); +} + +long test_fpcmpeq32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpeq32shl (a, b, 2); +} + +long test_fpcmpne32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpne32shl (a, b, 2); +} + +/* { dg-final { scan-assembler "fpcmple8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne8shl\t%" } } */ + +/* { dg-final { scan-assembler "fpcmple16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne16shl\t%" } } */ + +/* { dg-final { scan-assembler "fpcmple32shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt32shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpeq32shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpne32shl\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpurshl.c b/gcc/testsuite/gcc.target/sparc/fpcmpurshl.c new file mode 100644 index 00000000000..db74e01b5f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpurshl.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4b" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmpur8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpur8shl (a, b, 2); +} + +long test_fpcmpur16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpur16shl (a, b, 2); +} + +long test_fpcmpur32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpur32shl (a, b, 2); +} + +/* { dg-final { scan-assembler "fpcmpur8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpur16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpur32shl\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpushl.c b/gcc/testsuite/gcc.target/sparc/fpcmpushl.c new file mode 100644 index 00000000000..fc58deddb45 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpushl.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4b" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmpule8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpule8shl (a, b, 2); +} + +long test_fpcmpugt8shl (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpugt8shl (a, b, 2); +} + +long test_fpcmpule16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpule16shl (a, b, 2); +} + +long test_fpcmpugt16shl (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpugt16shl (a, b, 2); +} + +long test_fpcmpule32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpule32shl (a, b, 2); +} + +long test_fpcmpugt32shl (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpugt32shl (a, b, 2); +} + +/* { dg-final { scan-assembler "fpcmpule8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt8shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpule16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt16shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpule32shl\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt32shl\t%" } } */ diff --git a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/do-test.S b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/do-test.S index 1395235fd1e..ffe011bcc68 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/do-test.S +++ b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/do-test.S @@ -23,141 +23,101 @@ a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ -#ifdef __x86_64__ - -# ifdef __ELF__ -# define ELFFN_BEGIN(fn) .type fn,@function -# define ELFFN_END(fn) .size fn,.-fn -# else -# define ELFFN_BEGIN(fn) -# define ELFFN_END(fn) -# endif - -# define FUNC(fn) \ - .global fn; \ - ELFFN_BEGIN(fn); \ -fn: - -#define FUNC_END(fn) ELFFN_END(fn) - -# ifdef __AVX__ -# define MOVAPS vmovaps -# else -# define MOVAPS movaps -# endif - -/* TODO: Is there a cleaner way to provide these offsets? */ - .struct 0 -test_data_save: - - .struct test_data_save + 224 -test_data_input: - - .struct test_data_save + 448 -test_data_output: - - .struct test_data_save + 672 -test_data_fn: - - .struct test_data_save + 680 -test_data_retaddr: +#if defined(__x86_64__) && defined(__SSE2__) + +/* These macros currently support GNU/Linux, Solaris and Darwin. */ + +#ifdef __ELF__ +# define FN_TYPE(fn) .type fn,@function +# define FN_SIZE(fn) .size fn,.-fn +#else +# define FN_TYPE(fn) +# define FN_SIZE(fn) +#endif + +#ifdef __USER_LABEL_PREFIX__ +# define ASMNAME2(prefix, name) prefix ## name +# define ASMNAME1(prefix, name) ASMNAME2(prefix, name) +# define ASMNAME(name) ASMNAME1(__USER_LABEL_PREFIX__, name) +#else +# define ASMNAME(name) name +#endif + +#define FUNC_BEGIN(fn) \ + .globl ASMNAME(fn); \ + FN_TYPE (ASMNAME(fn)); \ +ASMNAME(fn): + +#define FUNC_END(fn) FN_SIZE(ASMNAME(fn)) + +#ifdef __AVX__ +# define MOVAPS vmovaps +#else +# define MOVAPS movaps +#endif .text -regs_to_mem: - MOVAPS %xmm6, (%rax) - MOVAPS %xmm7, 0x10(%rax) - MOVAPS %xmm8, 0x20(%rax) - MOVAPS %xmm9, 0x30(%rax) - MOVAPS %xmm10, 0x40(%rax) - MOVAPS %xmm11, 0x50(%rax) - MOVAPS %xmm12, 0x60(%rax) - MOVAPS %xmm13, 0x70(%rax) - MOVAPS %xmm14, 0x80(%rax) - MOVAPS %xmm15, 0x90(%rax) - mov %rsi, 0xa0(%rax) - mov %rdi, 0xa8(%rax) - mov %rbx, 0xb0(%rax) - mov %rbp, 0xb8(%rax) - mov %r12, 0xc0(%rax) - mov %r13, 0xc8(%rax) - mov %r14, 0xd0(%rax) - mov %r15, 0xd8(%rax) +FUNC_BEGIN(regs_to_mem) + MOVAPS %xmm6, (%r10) + MOVAPS %xmm7, 0x10(%r10) + MOVAPS %xmm8, 0x20(%r10) + MOVAPS %xmm9, 0x30(%r10) + MOVAPS %xmm10, 0x40(%r10) + MOVAPS %xmm11, 0x50(%r10) + MOVAPS %xmm12, 0x60(%r10) + MOVAPS %xmm13, 0x70(%r10) + MOVAPS %xmm14, 0x80(%r10) + MOVAPS %xmm15, 0x90(%r10) + mov %rsi, 0xa0(%r10) + mov %rdi, 0xa8(%r10) + mov %rbx, 0xb0(%r10) + mov %rbp, 0xb8(%r10) + mov %r12, 0xc0(%r10) + mov %r13, 0xc8(%r10) + mov %r14, 0xd0(%r10) + mov %r15, 0xd8(%r10) retq - -mem_to_regs: - MOVAPS (%rax), %xmm6 - MOVAPS 0x10(%rax),%xmm7 - MOVAPS 0x20(%rax),%xmm8 - MOVAPS 0x30(%rax),%xmm9 - MOVAPS 0x40(%rax),%xmm10 - MOVAPS 0x50(%rax),%xmm11 - MOVAPS 0x60(%rax),%xmm12 - MOVAPS 0x70(%rax),%xmm13 - MOVAPS 0x80(%rax),%xmm14 - MOVAPS 0x90(%rax),%xmm15 - mov 0xa0(%rax),%rsi - mov 0xa8(%rax),%rdi - mov 0xb0(%rax),%rbx - mov 0xb8(%rax),%rbp - mov 0xc0(%rax),%r12 - mov 0xc8(%rax),%r13 - mov 0xd0(%rax),%r14 - mov 0xd8(%rax),%r15 +FUNC_END(regs_to_mem) + +FUNC_BEGIN(mem_to_regs) + MOVAPS (%r10), %xmm6 + MOVAPS 0x10(%r10),%xmm7 + MOVAPS 0x20(%r10),%xmm8 + MOVAPS 0x30(%r10),%xmm9 + MOVAPS 0x40(%r10),%xmm10 + MOVAPS 0x50(%r10),%xmm11 + MOVAPS 0x60(%r10),%xmm12 + MOVAPS 0x70(%r10),%xmm13 + MOVAPS 0x80(%r10),%xmm14 + MOVAPS 0x90(%r10),%xmm15 + mov 0xa0(%r10),%rsi + mov 0xa8(%r10),%rdi + mov 0xb0(%r10),%rbx + mov 0xb8(%r10),%rbp + mov 0xc0(%r10),%r12 + mov 0xc8(%r10),%r13 + mov 0xd0(%r10),%r14 + mov 0xd8(%r10),%r15 retq +FUNC_END(mem_to_regs) # NOTE: Not MT safe -FUNC(do_test_unaligned) - .cfi_startproc +FUNC_BEGIN(do_test_unaligned) # The below alignment checks are to verify correctness of the test # its self. # Verify that incoming stack is aligned + 8 - pushf - test $0x8, %rsp - jne L0 + test $0xf, %rsp + je ASMNAME(do_test_body) int $3 # Stack not unaligned +FUNC_END(do_test_unaligned) -FUNC(do_test_aligned) +FUNC_BEGIN(do_test_aligned) # Verify that incoming stack is aligned - pushf - test $0xf, %rsp - je L0 + test $0x8, %rsp + jne ASMNAME(do_test_body) int $3 # Stack not aligned -L0: - popf - - # Save registers - lea test_data(%rip), %rax - call regs_to_mem - - # Load register with random data - lea test_data + test_data_input(%rip), %rax - call mem_to_regs - - # Save original return address - pop %rax - movq %rax, test_data + test_data_retaddr(%rip) - - # Call the test function - call *test_data + test_data_fn(%rip) - - # Restore the original return address - movq test_data + test_data_retaddr(%rip), %rcx - push %rcx - - # Save test function return value and store resulting register values - push %rax - lea test_data + test_data_output(%rip), %rax - call regs_to_mem - - # Restore registers - lea test_data(%rip), %rax - call mem_to_regs - pop %rax - retq - .cfi_endproc FUNC_END(do_test_aligned) -FUNC_END(do_test_unaligned) #endif /* __x86_64__ */ diff --git a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.c b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.c index 2a011f5103d..5fdd1e20674 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.c +++ b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.c @@ -46,6 +46,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see is then called. After the function returns, the value of all volatile registers is verified against the random data and then restored. */ +/* { dg-do run } */ +/* { dg-additional-sources "do-test.S" } */ +/* { dg-additional-options "-Wall" } */ + #include <stdio.h> #include <string.h> #include <stdlib.h> @@ -58,8 +62,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #include <errno.h> #include <ctype.h> -#ifndef __x86_64__ -# error Test only valid on x86_64 +#if !defined(__x86_64__) || !defined(__SSE2__) +# error Test only valid on x86_64 with -msse2 #endif enum reg_data_sets @@ -144,6 +148,72 @@ static __attribute__((ms_abi)) long static int arbitrarily_fail; static const char *argv0; + +#define PASTE_STR2(a) #a +#define PASTE_STR1(a, b) PASTE_STR2(a ## b) +#define PASTE_STR(a, b) PASTE_STR1(a, b) + +#ifdef __USER_LABEL_PREFIX__ +# define ASMNAME(name) PASTE_STR(__USER_LABEL_PREFIX__, name) +#else +# define ASMNAME(name) #name +#endif + +#ifdef __MACH__ +# define LOAD_TEST_DATA_ADDR(dest) \ + " mov " ASMNAME(test_data) "@GOTPCREL(%%rip), " dest "\n" +#else +# define LOAD_TEST_DATA_ADDR(dest) \ + " lea " ASMNAME(test_data) "(%%rip), " dest "\n" +#endif + +#define TEST_DATA_OFFSET(f) ((int)__builtin_offsetof(struct test_data, f)) + +void __attribute__((naked)) +do_test_body (void) +{__asm__ ( + " # rax, r10 and r11 are usable here.\n" + "\n" + " # Save registers.\n" + LOAD_TEST_DATA_ADDR("%%rax") + " lea %p0(%%rax), %%r10\n" + " call " ASMNAME(regs_to_mem) "\n" + "\n" + " # Load registers with random data.\n" + " lea %p1(%%rax), %%r10\n" + " call " ASMNAME(mem_to_regs) "\n" + "\n" + " # Pop and save original return address.\n" + " pop %%r10\n" + " mov %%r10, %p4(%%rax)\n" + "\n" + " # Call the test function, after which rcx, rdx and r8-11\n" + " # become usable.\n" + " lea %p3(%%rax), %%rax\n" + " call *(%%rax)\n" + "\n" + " # Store resulting register values.\n" + LOAD_TEST_DATA_ADDR("%%rcx") + " lea %p2(%%rcx), %%r10\n" + " call " ASMNAME(regs_to_mem) "\n" + "\n" + " # Push the original return address.\n" + " lea %p4(%%rcx), %%r10\n" + " push (%%r10)\n" + "\n" + " # Restore registers.\n" + " lea %p0(%%rcx), %%r10\n" + " call " ASMNAME(mem_to_regs) "\n" + "\n" + " retq\n" + :: + "i"(TEST_DATA_OFFSET(regdata[REG_SET_SAVE])), + "i"(TEST_DATA_OFFSET(regdata[REG_SET_INPUT])), + "i"(TEST_DATA_OFFSET(regdata[REG_SET_OUTPUT])), + "i"(TEST_DATA_OFFSET(fn)), + "i"(TEST_DATA_OFFSET(retaddr)) : "memory"); +} + static void __attribute__((noinline)) init_test (void *fn, const char *name, enum alignment_option alignment, enum shrink_wrap_option shrink_wrap, long ret_expected) diff --git a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.exp b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.exp index 26777e0b59f..87f81690bc7 100644 --- a/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.exp +++ b/gcc/testsuite/gcc.target/x86_64/abi/ms-sysv/ms-sysv.exp @@ -56,52 +56,48 @@ proc host_supports_c++11 {} { # Exit immediately if this isn't a native x86_64 target. if { (![istarget x86_64-*-*] && ![istarget i?86-*-*]) - || ![is-effective-target lp64] || ![isnative] - || ![host_supports_c++11] } then { - unsupported "$subdir" + || ![is-effective-target lp64] || ![isnative] + || ![host_supports_c++11] } then { + + # Gate "unsupported" message return value of first runtest_file_p call. + if [runtest_file_p $runtests "$srcdir/$subdir/ms-sysv.c"] { + unsupported "$subdir" + } return } -global GCC_RUNTEST_PARALLELIZE_DIR - proc runtest_ms_sysv { cflags generator_args } { global GCC_UNDER_TEST HOSTCXX HOSTCXXFLAGS tmpdir srcdir subdir \ - parallel_dir next_test + TEST_ALWAYS_FLAGS runtests set objdir "$tmpdir/ms-sysv" set generator "$tmpdir/ms-sysv-generate.exe" set generated_header "$objdir/ms-sysv-generated.h" - set do_test_o "$objdir/do-test.o" - set ms_sysv_o "$objdir/ms-sysv.o" - set ms_sysv_exe "$objdir/ms-sysv.exe" set status 0 set warn_flags "-Wall" - set this_test $next_test - incr next_test - - # Do parallelization here - if [catch {set fd [open "$parallel_dir/$this_test" \ - [list RDWR CREAT EXCL]]} ] { - if { [lindex $::errorCode 1] eq "EEXIST" } then { - # Another job is running this test - return - } else { - error "Failed to open $parallel_dir/$this_test: $::errorCode" - set status 1 - } - } else { - close $fd - } # Detect when hard frame pointers are enabled (or required) so we know not # to generate bp clobbers. - if [regexp "^(.+ +| *)-(O0|fno-omit-frame-pointer|p|pg)( +.*)?$" \ - $cflags match] then { + if { [regexp "(^| )-(O0|fno-omit-frame-pointer|p|pg)( |$)" \ + "$TEST_ALWAYS_FLAGS $cflags" match] + || [istarget *-*-solaris*] } then { set generator_args "$generator_args --omit-rbp-clobbers" } - set descr "$subdir CFLAGS=\"$cflags\" generator_args=\"$generator_args\"" - verbose "$tmpdir: Running test $descr" 1 + # Add all other flags + set escaped_generator_args [regsub -all " " $generator_args "\\ "] + set cflags "$cflags\"-DGEN_ARGS=$escaped_generator_args\"" + + gcc_parallel_test_enable 1 + if ![runtest_file_p $runtests "$srcdir/$subdir/ms-sysv.c"] then { + return + } + + #verbose "runtest_ms_sysv $cflags" 0 + + # Make sure there's no previous header file so that we can't accidentally + # pass if generation fails. + file delete -force $generated_header # Cleanup any previous test in objdir file delete -force $objdir @@ -109,18 +105,16 @@ proc runtest_ms_sysv { cflags generator_args } { # Build the generator (only needs to be done once). set src "$srcdir/$subdir/gen.cc" - if { $status == 0 } then { - if { (![file exists "$generator"]) || ([file mtime "$generator"] - < [file mtime "$src"]) } { - # Temporarily switch to the environment for the host compiler. - restore_ld_library_path_env_vars - set cxx "$HOSTCXX $HOSTCXXFLAGS $warn_flags -std=c++11" - set status [remote_exec host "$cxx -o $generator $src"] - set status [lindex $status 0] - set_ld_library_path_env_vars - if { $status != 0 } then { - warning "Could not build $subdir generator" - } + if { (![file exists "$generator"]) || ([file mtime "$generator"] + < [file mtime "$src"]) } { + # Temporarily switch to the environment for the host compiler. + restore_ld_library_path_env_vars + set cxx "$HOSTCXX $HOSTCXXFLAGS $TEST_ALWAYS_FLAGS $warn_flags -std=c++11" + set status [remote_exec host "$cxx -o $generator $src"] + set status [lindex $status 0] + set_ld_library_path_env_vars + if { $status != 0 } then { + warning "Could not build $subdir generator" } } @@ -133,75 +127,26 @@ proc runtest_ms_sysv { cflags generator_args } { } } - set cc "$GCC_UNDER_TEST -I$objdir -I$srcdir/$subdir $cflags $warn_flags" - - # Assemble do-test.S - set src "$srcdir/$subdir/do-test.S" - if { $status == 0 } then { - set status [remote_exec build "$cc -c -o $do_test_o $src"] - set status [lindex $status 0] - if { $status != 0 } then { - warning "Could not assemble $src" - } - } - - # Build ms-sysv.c - set src "$srcdir/$subdir/ms-sysv.c" - if { $status == 0 } then { - set status [remote_exec build "$cc -c -o $ms_sysv_o $src" "" "" "" 1200] - set status [lindex $status 0] - if { $status != 0 } then { - warning "Could not build $src." - } - } - - # Link - if { $status == 0 } then { - set status [remote_exec build "$cc -o $ms_sysv_exe $ms_sysv_o $do_test_o"] - set status [lindex $status 0] - if { $status != 0 } then { - warning "Link failed." - } - } - - # Execute - if { $status == 0 } then { - set status [remote_exec build "$ms_sysv_exe"] - set status [lindex $status 0] - } - - if { $status != 0 } then { - fail $descr - } else { - pass $descr - } + gcc_parallel_test_enable 0 + dg-runtest $srcdir/$subdir/ms-sysv.c "$cflags" "-I$objdir -I$srcdir/$subdir $warn_flags" + gcc_parallel_test_enable 1 } dg-init -# Setup parallelization -set next_test 0 -set parallel_dir "$env(GCC_RUNTEST_PARALLELIZE_DIR)/abi-ms-sysv" -file mkdir "$env(GCC_RUNTEST_PARALLELIZE_DIR)" -file mkdir "$parallel_dir" - -if { ![file isdirectory "$parallel_dir"] } then { - error "Failed to create directory $parallel_dir: $::errorCode" - return -} +# Standard test parameters. +set gen_pcount_opts [list "-p0" "-p1" "-p5"] +set base_cflags_arr [list " -O2 " " -O0 -g3 "] -set gen_opts "-p0-5" -set all_options [list "-O2" "-O0 -g3"] +foreach gen_opts $gen_pcount_opts { + foreach cflags $base_cflags_arr { + # Run without -mcall-ms2sysv-xlogues always + runtest_ms_sysv "$cflags" "$gen_opts" -# Run without -mcall-ms2sysv-xlogues always -foreach opt $all_options { - runtest_ms_sysv "$opt" "$gen_opts" -} - -# Skip -mcall-ms2sysv-xlogues on Windows (not supported) -if { ![istarget *-*-cygwin*] && ![istarget *-*-mingw*] } { - foreach opt $all_options { - runtest_ms_sysv "-mcall-ms2sysv-xlogues $opt" "$gen_opts" + # Skip unsupported -mcall-ms2sysv-xlogues on Windows + if { ![istarget *-*-cygwin*] && ![istarget *-*-mingw*] } { + runtest_ms_sysv "-mcall-ms2sysv-xlogues$cflags" "$gen_opts" + } } } |